Double Data Rate Flip-Flops

Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)

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1.5 English
Each pin contains local double-data rate (DDR) flip-flop registers in the IOL for both data and tristate lines. IDDRE1 should be used for instantiating DDR flip-flops in the input path while ODDRE1 should be used for output and tristate paths.
Note: Both data and tristate registers must be used in the same manner (that is both SDR, DDR, or not registered at all).