Clocking Resources

Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)

Document ID
Release Date
1.5 English

Each XPIO bank has access to four clock managers as well as to several global clock buffers which can aid in XPIO interfaces by providing clock frequency synthesis, jitter filtering, and clock deskew. Because these resources are described in detail in Versal Adaptive SoC Clocking Resources Architecture Manual (AM003), deeper level details are not covered in this chapter.

As mentioned in Clocking, there are four global clock (GC) inputs per XPIO bank which have direct access to clock routing resources through global clock buffers as well as having direct access to adjacent clock managers. Each of the four GC pins can be used as a single-ended clock or as a P-side (master) of a differential pair to drive adjacent clock managers or global clock buffers.

In each XPIO banks exist two XPLL clocking managers. The XPLL provides a user-controlled phase and deskew control and an optimized connection to the XPHY, but can also be used with the XP IOL. Refer to XP XPHY Architecture for details on how the XPLL resources are used with the XPHY.

In addition to the two XPLL, adjacent to each XPIO bank are MMCM and DPLL clock mangers. The MMCM provides a deskew phase detector and extensive frequency synthesis capabilities which can be useful in XPIO interface clocking. The DPLL provides similar functionality as the MMCM but with reduced functionality related to fractional clock generation. Both the MMCM and DPLL can be used in XPIO interfaces to synthesize and deskew clock sources.

Besides clock managers, GC input pins have several options for driving global clock buffers directly or through the clock managers described above. Adjacent to each XPIO bank are 24 BUFGCEs, 8 BUFGCTRLS, and 4 BUFGCE_DIVs.