XP IOB Supported Standards

Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)
Document ID
AM010
Release Date
2024-03-18
Revision
1.5 English

See the XP IOB Internal VREF section for more information on the INTERNAL VREF, DRIVE, and TERMINATION options listed in the following table.

Table 1. Single-Ended Standards Available in the XP IOB
IOSTANDARD Required VCCO Level for Input and Output Required INTERNAL_VREF Level for Input Drive and Termination Options
LVCMOS12 1.2V N/A DRIVE: 2, 4, 6, 8
LVCMOS15 1.5V N/A DRIVE: 2, 4, 6, 8, 12
LVDCI_15 1.5V N/A OUTPUT_IMPEDANCE
LVSTL_11 1.1V 0.183V OUTPUT_IMPEDANCE, ODT(SINGLE to GND)
LVSTL06_12 1.2V 0.125V OUTPUT_IMPEDANCE, ODT(SINGLE to GND)
HSUL_12 1.2V 0.60V OUTPUT_IMPEDANCE, ODT(SINGLE to VCCO)
HSLVDCI_15 1.5V 0.75V OUTPUT_IMPEDANCE, ODT(SPLIT)
HSTL_I 1.5V 0.75V OUTPUT_IMPEDANCE, ODT(SPLIT)
HSTL_I_12 1.2V 0.60V OUTPUT_IMPEDANCE, ODT(SPLIT)
POD12 1.2V 0.84V OUTPUT_IMPEDANCE, ODT(SINGLE to VCCO)
POD10 1.0V 0.70V OUTPUT_IMPEDANCE, ODT(SINGLE to VCCO)
SSTL12 1.2V 0.60V OUTPUT_IMPEDANCE, ODT(SPLIT)
SSTL15 1.5V 0.75V OUTPUT_IMPEDANCE, ODT(SPLIT)
SSTL135 1.35V 0.675V OUTPUT_IMPEDANCE, ODT(SPLIT)
Important: In the Vivado tools, the default standard assigned to an IOB is UNDEFINED (or DIFF_UNDEFINED for differential buffers). The IOSTANDARD UNDEFINED has no actual meaning in the IOB and the Vivado tools will not generate a valid programming file if it is not changed to a valid IOSTANDARD.

See the Calibrated Termination (Digitally Controlled Impedance) section for more information on the DRIVE and TERMINATION options listed in the following table.

Table 2. Differential Standards Available in the XP IOB
IOSTANDARD VCCO Level Drive and Termination Options
DIFF_SSTL15 1 1.5V OUTPUT_IMPEDANCE, ODT(SPLIT)
DIFF_SSTL135 1 1.35V OUTPUT_IMPEDANCE, ODT(SPLIT)
DIFF_SSTL12 1 1.2V OUTPUT_IMPEDANCE, ODT(SPLIT)
DIFF_HSUL_12 1 1.2V OUTPUT_IMPEDANCE, ODT(SINGLE to VCCO)
LVDS15 1 1.5V DIFF_TERM_ADV
DIFF_HSTL_I 1 1.5V OUTPUT_IMPEDANCE, ODT(SPLIT)
DIFF_HSTL_I_12 1 1.2V OUTPUT_IMPEDANCE, ODT(SPLIT)
DIFF_LVSTL_11 1.1V OUTPUT_IMPEDANCE, ODT(SINGLE to GND)
DIFF_LVSTL06_12 1.2V OUTPUT_IMPEDANCE, ODT(SINGLE to GND)
DIFF_POD10 1.0V OUTPUT_IMPEDANCE, ODT(SINGLE to VCCO)
DIFF_POD12 1.2V OUTPUT_IMPEDANCE, ODT(SINGLE to VCCO)
MIPI_DPHY 1.2V OUTPUT_IMPEDANCE, DIFF_TERM_ADV
  1. Differential inputs for these standards can be placed in banks with VCCO levels that are different from the required level for outputs. Some important criteria to consider:
    • The optional internal differential termination is not used: DIFF_TERM_ADV = TERM_NONE or ODT = RTT_NONE.
    • DQS_BIAS should not be used (DQS_BIAS = FALSE) because DQS_BIAS will bias to VCCO, which might not be appropriate for all interfaces.
    • The differential signals at the input pins meet the VIN requirements in the Recommended Operating Conditions table of the specific Versal adaptive SoC data sheets.
    • The differential signals at the input pins meet the VIDIFF and VICM requirements in the DC Specifications tables of the specific Versal adaptive SoC data sheets. In some cases, to accomplish this it might be necessary to provide an external circuit to both AC couple and DC bias the pins.