Controlling Tristate Control

Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)

Document ID
AM010
Release Date
2024-03-18
Revision
1.5 English
Buffers with tristate capability can be controlled through the XPHY on a per-NIBBLESLICE basis, as determined through the TBYTE_CTL_<0-5> attribute. The <0-5> suffix of TBYTE_CTL_<0-5> corresponds to the NIBBLESLICE it is applied to. So TBYTE_CTL_0 is the tristate control setting for NIBBLESLICE[0], TBYTE_CTL_1 corresponds to NIBBLESLICE[1], and so on.
TBYTE_CTL_x = T
Uses the T[x] input of the XPHY to drive the tristate control signal to the IOB of NIBBLESLICE[x]. This is a combinatorial path from the PL and thus is not aligned to TX data. When TX_DATA_WIDTH = 2, this is the only TBYTE_CTL_x setting supported.
TBYTE_CTL_x = PHY_WREN
Inverts and serializes the PHY_WREN input of the XPHY to drive (broadcast) the tristate control signal to the IOB of each NIBBLESLICE. Each bit of PHY_WREN acts as the tristate control signal for two UIs worth of data. The serialized and inverted PHY_WREN signal is aligned to the serialized output of the TX datapath, O0. PHY_WREN cannot be used when TX_DATA_WIDTH = 2.

TBYTE_CTL_x determines which signal, T or PHY_WREN, is accepted by NIBBLESLICE[x]. For example, if NIBBLESLICE[0] receives both a PHY_WREN and T stimulus, only the one matching TBYTE_CTL_0 is accepted. T_OUT[x] is then the output to the IOB.

The latency through the TX datapath is shown for TBYTE_CTL_x = PHY_WREN. PHY_WREN takes one cycle longer than the data to propagate through the XPHY. Due to this, PHY_WREN should be applied one cycle before TX data is presented to the XPHY from the PL.

Note: Updates to the delay line in tristate control must be done through the RIU interface.

When using TBYTE_CTL = PHY_WREN, the T_OUT routing delays to the IOB are longer than the O0 routing delays as shown in the following figure.

Figure 1. XPHY to IOB Tristate Routing

Due to the routing differences between T_OUT and O0, the initial data bit being transmitted might be shortened in length. As shown in the following figure, the tristate control arrives after data, causing the first data bit being transmitted to be shortened. In this example, the shortened data bit has been addressed by adding a preamble cycle with the data matching the first bit. The shortened data bit could be fixed by adding a preamble that matches the first data bit and control T_OUT so the preamble drives out the preamble.

Figure 2. Tristate With IOB Delays And Preamble

Independent of tristating, each bit of O0 maps to one of the D<0-5>[7:0] inputs. Generalized, this means Dx maps to O0[x]. The following tables shows how Dx maps to O0[x] for different data widths. Refer to the latency waveforms below for the context of P0, N0, …, P3, N3.

Table 1. Dx to O0[x] Mapping
Serialization (TX_DATA_WIDTH) Dx
Dx[7] Dx[6] Dx[5] Dx[4] Dx[3] Dx[2] Dx[1] Dx[0]
8:1 The eighth bit serialized and transmitted through O0[x] The seventh bit serialized and transmitted through O0[x] The sixth bit serialized and transmitted through O0[x] The fifth bit serialized and transmitted through O0[x] The fourth bit serialized and transmitted through O0[x] The third bit serialized and transmitted through O0[x] The second bit serialized and transmitted through O0[x] The first bit serialized and transmitted through O0[x]
4:1 The fourth bit serialized and transmitted through O0[x] The third bit serialized and transmitted through O0[x] The second bit serialized and transmitted through O0[x] The first bit serialized and transmitted through O0[x]
2:1 The second bit serialized and transmitted through O0[x] The first bit serialized and transmitted through O0[x]

Dx and O0 in the following figures refer to a single NIBBLESLICE. Dx maps to one of the O0[x] outputs.

Figure 3. 8-Bit TX Latency with Tristate Control (TBYTE_CTL_x = PHY_WREN)
Figure 4. 4-Bit TX Latency with Tristate Control (TBYTE_CTL_x = PHY_WREN)

The latency through the TX datapath when NOT using tristate control or when TBYTE_CTL_x = T is shown in the following figures.

Figure 5. 8-Bit TX Latency
Figure 6. 4-Bit TX Latency
Figure 7. 2-Bit TX Latency