Uncalibrated Output Delay Primitive

Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)

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Figure 1. ODELAYE5

Table 1. ODELAYE5 Attributes
Attribute Values Description
CASCADE FALSE, TRUE The CASCADE attribute is set to TRUE when the ODELAYE5 is used to cascade the IDELAYE5. This attribute enables a delay greater than 1.8 ns.
Table 2. ODELAYE5 Ports
Port I/O Description
DATAOUT Output Delayed data to the pin. When cascading the ODELAYE5 to the IDELAYE5, DATAOUT should be connected to the CASC_RETURN pin of the IDELAYE5.
CNTVALUEOUT<4:0> Output The CNTVALUEOUT pins are used for reporting the current tap value and reads out the amount of taps in the current delay.
TDATAOUT Output Delayed tristate control connects to the IOB.
CASC_IN Input Cascade delay from IDELAYE5 CASC_OUT. The CASC_IN pin is used when cascading the ODELAYE5 delay to the IDELAYE5.
ODATAIN Input Delayed data to the IOB.
CNTVALUEIN<4:0> Input The CNTVALUEIN pins are used for dynamically switching the loadable tap value. The CNTVALUEIN is the number of taps required.
CE Input Clock enable used with INC port to increment (INC=1) or decrement (INC=0) the delay line. Leaving CE enabled for multiple CLK cycles will allow consecutive changes in the delay value.
CLK Input Clock used to sample LOAD, CE, and INC.
INC Input Increment and decrement are controlled by the enable signal (CE).
  • INC = 1 increments
  • INC = 0 decrements
LOAD Input Load counter value from the CNTVALUEIN bus when High.
RST Input The reset pin (RST) is asynchronous with the CLK.
TDATAIN Input Tristate control input.