HD IOB Banking Structure

The HDIO pins are grouped into banks of 22 IOBs (11 I/O pairs) and a DPLL. Each IOB has an independent HD IOL logic block. All IOBs in an HD bank share the same V_CCO power supply to power driver logic, receiver logic, and termination. Regardless of whether the IOB is used as an input, output, or bi-directional pin, each I/O standard has a specific V_CCO voltage requirement that must be adhered to for the I/O standard to populate a bank. Each HD bank has two dedicated pins with direct access to a clock buffer, referred to as HDGC pins, which allow for distribution of the clock to the rest of the bank. The HDIO bank's DPLL provides clock deskew capabilities to a HDIO bank. For more details on the DPLL, see Versal Adaptive SoC Clocking Resources Architecture Manual (AM003).