HD IOB Banking Structure

Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)

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1.5 English
The HDIO pins are grouped into banks of 22 IOBs (11 I/O pairs) and a DPLL. Each IOB has an independent HD IOL logic block. All IOBs in an HD bank share the same VCCO power supply to power driver logic, receiver logic, and termination. Regardless of whether the IOB is used as an input, output, or bi-directional pin, each I/O standard has a specific VCCO voltage requirement that must be adhered to for the I/O standard to populate a bank. Each HD bank has two dedicated pins with direct access to a clock buffer, referred to as HDGC pins, which allow for distribution of the clock to the rest of the bank. The HDIO bank's DPLL provides clock deskew capabilities to a HDIO bank. For more details on the DPLL, see Versal Adaptive SoC Clocking Resources Architecture Manual (AM003).
Figure 1. HD Bank (22 I/O, 11 I/O pairs, 2 Clock-capable Pins, 1 DPLL)