XP IOB Supported Differential Standards

Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)
Document ID
AM010
Release Date
2024-03-18
Revision
1.5 English

DIFF_SSTL

The stub-series terminated logic (SSTL) for 1.5V (DIFF_SSTL15) and 1.35V (DIFF_SSTL135) are differential I/O standards used for general-purpose memory buses. DIFF_SSTL15 is used for DDR3 SDRAM interfaces and is roughly defined (not by name) in the JEDEC standard JESD79-3E. DIFF_SSTL135 is used for DDR3L SDRAM interfaces and is roughly defined (not by name) in the JEDEC standard JESD79-3-1.
Table 1. Allowed Attributes for DIFF_SSTL15, DIFF_SSTL135 and DIFF_SSTL12 I/O Primitives
Attributes IBUFDS/IBUFDSE3 OBUFDS/OBUFTDS IOBUFDS/IOBUFTDS
Allowed Values Default Allowed Value Default Allowed Values Default
IOSTANDARD DIFF_SSTL15, DIFF_SSTL135, DIFF_SSTL12 DIFF_SSTL15, DIFF_SSTL135, DIFF_SSTL12 DIFF_SSTL15, DIFF_SSTL135, DIFF_SSTL12
SLEW N/A FAST, MEDIUM, SLOW SLOW FAST, MEDIUM, SLOW SLOW
OUTPUT_IMPEDANCE N//A RDRV_40_40, RDRV_48_48, RDRV_60_60 RDRV_40_40 RDRV_40_40, RDRV_48_48, RDRV_60_60 RDRV_40_40
ODT RTT_40, RTT_48, RTT_60, RTT_NONE (DIFF_SSTL12 only) RTT_40, RTT_NONE (DIFF_SSTL12 only) N/A RTT_40, RTT_48, RTT_60, RTT_NONE (DIFF_SSTL12 only) RTT_40, RTT_NONE (DIFF_SSTL12 only)
DQS_BIAS (DIFF_SSTL12 ONLY) TRUE, FALSE FALSE   TRUE, FALSE FALSE
VOH (DIFF_SSTL15 ONLY) N/A N/A 75, 80 75 N/A N/A

DIFF_HSUL12

The high-speed unterminated logic (HSUL) DIFF_HSUL12 differential standard is optimized for lower-power memory interfaces.
Table 2. Allowed Attributes for DIFF_HSUL_12 and I/O Primitives
Attributes IBUFDS/IBUFDSE3 OBUFDS/OBUFTDS IOBUFDS/IOBUFDSE3
Allowed Values Default Allowed Values Default Allowed Values Default
IOSTANDARD DIFF_HSUL_12 DIFF_HSUL_12 DIFF_HSUL_12
SLEW N/A FAST, MEDIUM, SLOW SLOW FAST, MEDIUM, SLOW SLOW
OUTPUT_IMPEDANCE N//A RDRV_40_40, RDRV_48_48, RDRV_60_60 RDRV_48_48 RDRV_40_40, RDRV_48_48, RDRV_60_60 RDRV_48_48
ODT RTT_120, RTT_240 RTT_120 N/A RTT_120, RTT_240 RTT_120

DIFF_LVSTL

The low-voltage swing terminated logic (DIFF_LVSTL_11 and DIFF_LVSTL06_12) standards are optimized for lower-power memory interfaces. DIFF_LVSTL06_12 is compatible with differential LVSTL06 interfaces but is powered at 1.2V.
Table 3. Allowed Attributes for DIFF_LVSTL_11 and DIFF_LVSTL06_12 and I/O Primitives
Attributes IBUFDS/IBUFDSE3 OBUFDS/OBUFTDS IOBUFDS/IOBUFDSE3
Allowed Values Default Allowed Values Default Allowed Values Default
IOSTANDARD DIFF_LVSTL_11, DIFF_LVSTL06_12 DIFF_LVSTL_11, DIFF_LVSTL06_12 DIFF_LVSTL_11, DIFF_LVSTL06_12
SLEW N/A FAST, MEDIUM, SLOW SLOW FAST, MEDIUM, SLOW SLOW
OUTPUT_IMPEDANCE N//A RDRV_40_40, RDRV_48_48 (DIFF_LVSTL_11 only), RDRV_60_60 RDRV_40_40 RDRV_40_40, RDRV_48_48 (DIFF_LVSTL_11 only), RDRV_60_60 RDRV_40_40
ODT RTT_40, RTT_48 (DIFF_LVSTL_11 only), RTT_60, RTT_NONE RTT_40 N/A RTT_40, RTT_48 (DIFF_LVSTL_11 only), RTT_60, RTT_NONE RTT_40
VOH (DIFF_ LVSTL_11 ONLY) N/A 50 50 50 50
PRE_EMPHASIS N/A   RDRV_240 (DIFF_LVSTL_11 only), RDRV_NONE RDRV_NONE
EQUALIZATION EQ_LEVEL0, EQ_LEVEL1, EQ_LEVEL2, EQ_LEVEL3, EQ_LEVEL4, EQ_NONE EQ_NONE   N/A
DC_BIAS DC_BIAS_0, DC_BIAS1, DC_BIAS2, DC_BIAS3 DC_BIAS_0   DC_BIAS_0, DC_BIAS1, DC_BIAS2, DC_BIAS3 DC_BIAS_0

LVDS

LVDS15 is a 1.5V powered standard designed to interface with the low-voltage differential signaling (LVDS) standard. It is compatible with EIA/TIA electrical specifications but is powered at 1.5V to operate within the XPIO bank architecture.
Table 4. Allowed Attributes for LVDS15 and I/O Primitives
Attributes IBUFDS/IBUFDSE3 OBUFDS/OBUFTDS IOBUFDS/IOBUFDSE3 1
Allowed Values Default Allowed Values Default Allowed Values Default
IOSTANDARD LVDS15 LVDS15 LVDS15
DIFF_TERM_ADV TERM_100, TERM_NONE TERM_NONE N/A TERM_100, TERM_NONE TERM_NONE
LVDS_PRE_EMPHASIS N/A FALSE, TRUE FALSE FALSE, TRUE FALSE
EQUALIZATION EQ_LEVEL0, EQ_LEVEL1, EQ_LEVEL2, EQ_LEVEL3, EQ_LEVEL4, EQ_NONE EQ_NONE   N/A
DC_BIAS DC_BIAS_0, DC_BIAS1, DC_BIAS2, DC_BIAS3 DC_BIAS_0   DC_BIAS_0, DC_BIAS1, DC_BIAS2, DC_BIAS3 DC_BIAS_0
  1. The bidirectional configuration on these I/O standards is a fixed impedance structure optimized to 100Ω differential. They are only intended to be used in point-to-point transmissions that do not have turn around timing requirements. Bidirectional interfaces should only be used when longer turnaround times can be tolerated.

DIFF_HSTL

DIFF_HSTL_I (1.5V) and DIFF_HSTL_I_12 (1.2V) are both differential high-speed transceiver logic (HSTL) standards used for the general-purpose high-speed bus standards defined by the JEDEC standard JESD8-6.
Table 5. Allowed Attributes for DIFF_HSTL_I and DIFF_HSTL_I_12 I/O Primitives
Attributes IBUFDS/IBUFDSE3 OBUFDS/OBUFTDS IOBUFDS/IOBUFDSE3
Allowed Values Default Allowed Values Default Allowed Values Default
IOSTANDARD DIFF_HSTL_I, DIFF_HSTL_I_12 DIFF_HSTL_I, DIFF_HSTL_I_12 DIFF_HSTL_I, DIFF_HSTL_I_12
ODT RTT_40, RTT_48, RTT_60 RTT_48 N/A RTT_40, RTT_48, RTT_60 RTT_48
OUTPUT_IMPEDANCE N//A RDRV_40_40, RDRV_48_48, RDRV_60_60 RDRV_48_48 RDRV_40_40, RDRV_48_48, RDRV_60_60 RDRV_48_48
SLEW N/A FAST, MEDIUM, SLOW SLOW FAST, MEDIUM, SLOW SLOW

DIFF_POD

The differential (DIFF_) versions (DIFF_POD10 and DIFF_POD12) use complementary single-ended drivers for outputs and differential receivers for inputs.
Table 6. Allowed Attributes for DIFF_POD10 and DIFF_POD12 I/O Primitives
Attributes IBUFDS/IBUFDSE3 OBUFDS/OBUFTDS IOBUFDS/IOBUFDSE3
Allowed Values Default Allowed Value Default Allowed Values Default
IOSTANDARD DIFF_POD10, DIFF_POD12 DIFF_POD10, DIFF_POD12 DIFF_POD10, DIFF_POD12
SLEW N/A FAST, MEDIUM, SLOW SLOW FAST, MEDIUM, SLOW SLOW
OUTPUT_IMPEDANCE N//A RDRV_40_40, RDRV_48_48, RDRV_60_60 RDRV_40_40 RDRV_40_40, RDRV_48_48, RDRV_60_60 RDRV_40_40
ODT RTT_40, RTT_48, RTT_60 RTT_40 N/A RTT_40, RTT_48, RTT_60 RTT_40
PRE_EMPHASIS N/A RDRV_240, RDRV_NONE RDRV_NONE RDRV_240, RDRV_NONE RDRV_NONE
EQUALIZATION (DIFF_POD12 ONLY) EQ_LEVEL0, EQ_LEVEL1, EQ_LEVEL2, EQ_LEVEL3, EQ_LEVEL4, EQ_NONE EQ_NONE N/A N/A
DQS_BIAS (DIFF_POD12 ONLY) TRUE, FALSE FALSE   TRUE, FALSE FALSE

MIPI_DPHY

The MIPI D-PHY standard MIPI_DPHY is intended for use in mobile devices including cameras, displays, and unified protocol interfaces.
Table 7. Allowed Attributes for MIPI_DPHY I/O Primitives
Attributes IBUFDS_DPHY OBUFDS_DPHY
Allowed Values Default Allowed Value Default
IOSTANDARD MIPI_DPHY MIPI_DPHY
DIFF_TERM_ADV TERM_100, TERM_NONE TERM_NONE N/A
VOH N//A 28 28
PRE_EMPHASIS N/A RDRV_480, RDRV_NONE RDRV_NONE
EQUALIZATION EQ_LEVEL0, EQ_LEVEL1, EQ_LEVEL2, EQ_LEVEL3, EQ_LEVEL4, EQ_LEVEL5, EQ_LEVEL6, EQ_LEVEL7, EQ_LEVEL8. EQ_NONE EQ_NONE  

DIFF_UNDEFINED Default IOSTANDARD

When an IOSTANDARD is not defined by the user, the default assignment for the IOSTANDARD defaults to DIFF_UNDEFINED. For a Versal device design to complete implementation, a non-default IOSTANDARD must be defined with one of the valid I/O standards described in this section. The DIFF_UNDEFINED standard acts as a placeholder to allow a design to complete the early stages of implementation.