Bidirectional Datapath

Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)

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The TX and RX datapaths within each XPHY NIBBLESLICE can be used together to form a bidirectional datapath. As shown in Figure 3, each TX datapath drives both to the pad and the RX datapath. As such, care must be taken when using the bidirectional datapath so as to tristate the buffer or gate the datapaths without data loss.

The XPHY offers transmit gating, receive gating, and tristating as mechanisms to control the bidirectional datapath. See the table below for a summary of how to enable these controls through the XPHY attributes.

Table 1. Enabling Bidirectional Datapath Control
Control Mechanism Related Attributes
RX datapath gating
The RX_GATING attribute enables gating of the RX datapath based on the PHY_RDEN port. While RX_GATING enables gating, the CONTINUOUS_DQS attribute lets users choose between PHY_RDEN operating based in the PLL_CLK or the strobe clock domain.
TX datapath gating
The TX_GATING attribute enables gating of the TX datapath based on the PHY_WREN port (which is serialized but not inverted when used for gating) and PHY_WREN operates in the PLL_CLK domain. NIBBESLICE[1] cannot be gated.
The TBYTE_CTL_# attribute determines whether tristating is controlled by the T (combinatorial) port or an inverted and serialized PHY_WREN port (which is in the PLL_CLK domain).

T_OUT[5:0] is the tristate control output from the XPHY. Each bit of T_OUT is associated with a NIBBLESLICE, and TBYTE_CTL_# allows each NIBBLESLICE to select its corresponding T_OUT bit to be controlled by either T or PHY_WREN. In other words for a NIBBLESLICE[x], T_OUT[x] reflects the tristate control input selected by TBYTE_CTL_x. If TBYTE_CTL_x = T, T_OUT[x] (associated with NIBBLESLICE[x]) is controlled via the T[x] input. Because this is a combinatorial route, T_OUT[x] is not aligned to the data. If TBYTE_CTL_x = PHY_WREN, T_OUT[x] (associated with NIBBLESLICE[x]) is controlled through the PHY_WREN port. This input is inverted, serialized, and output synchronously (through T_OUT[x]) with the TX data when used for tristating. For more information, see Controlling Tristate Control.

Important: When using 2:1 serialization (TX_DATA_WIDTH = 2), each NIBBLESLICE tristate buffer can only be controlled through the combinatorial T input (TBYTE_CTL_<0-5> = T). Tristate control through the PHY_WREN input (TBYTE_CTL_x = PHY_WREN) is only possible for 8:1 and 4:1 serialization (TX_DATA_WIDTH = 8 and 4, respectively).

PHY_RDEN is set up and used to control RX datapath gating is as follows:

  • PHY_RDEN controls accepting or rejecting the strobe entering on NIBBLESLICE[0] or from inter-byte clocking, depending upon the settings of CONTINUOUS_DQS, RX_GATING, and RX_DATA_WIDTH. Always ensure the strobe has stabilized and BISC has completed before asserting PHY_RDEN. Refer to Controlling Built-in Self-Calibration for when BISC is considered completed.
  • When RX_GATING = ENABLE, and CONTINUOUS_DQS = TRUE, and RX_DATA_WIDTH = don't care, then the four bits of PHY_RDEN are OR'd together and that output is used to control the gate. If the result of the OR operation is 1, the capture clock is accepted. If it is 0, then the capture clock is rejected. PHY_RDEN is synchronized to the capture clock for this attribute combination. When CONTINUOUS_DQS = TRUE, send 2 capture clock cycles before sending data.
  • When RX_GATING = ENABLE, CONTINUOUS_DQS = FALSE, and RX_DATA_WIDTH = 4 or 8, set the following bits of PHY_RDEN to 1 to accept the strobe or 0 to reject the strobe. PHY_RDEN is synchronized to PLL_CLK for this attribute combination. Each bit of PHY_RDEN controls two UI worth of data:
    • If RX_DATA_WIDTH = 8: [3:0]
    • If RX_DATA_WIDTH = 4: [2][0]
    • If RX_DATA_WIDTH = 2: not supported
  • When RX_GATING = DISABLE the gate is always open, regardless of the value of RX_DATA_WIDTH, CONTINUOUS_DQS, or PHY_RDEN. In this scenario (RX_GATING = DISABLE), the strobe starts the deserialization in the RX datapath. Because of this, the strobe must be stable to ensure XPHY alignment.
  • When SERIAL_MODE = TRUE, tie all four bits of PHY_RDEN High.

PHY_WREN is set up and used to control TX datapath gating as follows:

  • When TX_GATING = ENABLE, PHY_WREN gates the TX datapath of NIBBLESLICE[0], NIBBLESLICE[2], NIBBLESLICE[3], NIBBLESLICE[4], and NIBBLESLICE[5]. NIBBLESLICE[1] cannot be gated. Set the following bits of PHY_WREN to 0 to gate transmit data or 1 to not gate transmit data:
    • If TX_DATA_WIDTH = 8: [3:0]
    • If TX_DATA_WIDTH = 4: [2][0]
    • If TX_DATA_WIDTH = 2: not supported
  • Note that PHY_WREN can be used to control both TX datapath gating (if TX_GATING = ENABLE) and tristating (if TBYTE_CTL_# = PHY_WREN). However, only when PHY_WREN is used for tristating is it inverted and serialized prior to its use. When used for gating, PHY_WREN is serialized but is not inverted. Thus, when used for gating, PHY_WREN should be set to 1 to open the gate and 0 to close the gate. When used for tristating, PHY_WREN should be set to 0, which is then inverted to 1 to tristate the buffer. It follows that setting PHY_WREN to 1 for tristating results in the buffer not being tristated. See Controlling Tristate Control for more information on tristating.

Other important points to keep in mind:

  • When turning the bus around, toggle the BS_RESET_CTRL.clr_gate bit then toggle the BS_RESET_CTRL.bs_reset bit. Toggling BS_RESET_CTRL.clr_gate clears the strobe path gating logic, helping to ensure proper alignment when combined with the NIBBLESLICE reset performed through the toggling of BS_RESET_CTRL.bs_reset. After doing these resets the FIFO will be reset and FIFO_EMPTY will be asserted high. Continue reading this section for the bs_reset/clr_gate sequence. See Register Interface Unit for more information on BS_RESET_CTRL. After the write to bs_reset is completed, data can be transmitted immediately. For receivers, however, the first FIFO_EMPTY deassertion should be used to know when receiving valid data.
  • Before performing a bs_reset, set PHY_WREN and PHY_RDEN to 0 regardless of the TX_GATING or RX_GATING settings to ensure the alignment will be reset.
  • Setting CONTINUOUS_DQS = TRUE requires that two capture clock cycles be received prior to receiving data to prevent data loss.
  • If the TX-only interface data and clock, as well as bidirectional interface data, exist in the same nibble then TBYTE_CTL_# must be set to T for all pins in either interface, regardless of if they are part of the TX-only interface or bidirectional interface, and TX_GATING must be set to DISABLE.
  • If the TX-only interface clock is placed in NIBBLESLICE[1], TX_GATING can be set to ENABLE because NIBBLESLICE[1] cannot be gated. In this scenario, TBYTE_CTL_# should be set to PHY_WREN for the bidirectional pins in the nibble, and TBYTE_CTL_# should be set to T for the TX-only pins in the nibble. If the TX-only interface clock is not placed on NIBBLESLICE[1], TX_GATING must be set to DISABLE, and TBYTE_CTL_# must be set to T for all pins in the interfaces, regardless of whether they are TX-only or bidirectional.
  • When TX_DATA_WIDTH = 2 or RX_DATA_WIDTH = 2, bidirectional support is limited to:
    • TX_GATING must be set to DISABLE.
    • RX_GATING can be set to ENABLE, but only when CONTINUOUS_DQS is also set to TRUE.
    • Tristating is only supported through the T port (TBYTE_CTL_# = T).

To perform a clr_gate and bs_reset sequence to turn the bus around, do the following:

  1. Assert BS_RESET_CTRL.clr_gate through the RIU.
  2. Deassert BS_RESET_CTRL.clr_gate through the RIU. The strobe path gating logic is now clear.
  3. If PHY_WREN and PHY_RDEN have not already been set to 0, they must be set to 0 before continuing with this step. Assert BS_RESET_CTRL.bs_reset, which resets NIBBLESLICEs not masked by BS_RST_MASK.bs_reset_mask. While bs_reset is asserted, the TX IOBs of NIBBLESLICEs not masked by BS_RST_MASK.bs_reset_mask are set to the value of their associated TX_INIT_# attribute. Keep BS_RESET_CTRL.bs_reset asserted for a minimum number of clock cycles based on the TX_DATA_WIDTH and RX_DATA_WIDTH attributes:
    • For data width of 8: 1 CTRL_CLK cycle + 72 PLL_CLK cycles
    • For data width of 4: 1 CTRL_CLK cycle + 40 PLL_CLK cycles
    • For data width of 2: 1 CTRL_CLK cycle + 24 PLL_CLK cycles
  4. Deassert BS_RESET_CTRL.bs_reset. After the write to bs_reset is completed, data can be transmitted immediately. For receivers, however, the first FIFO_EMPTY deassertion should be used to know when receiving valid data. PHY_RDEN and PHY_WREN can now be changed from 0.
Important: If receiving a strobe (implying CONTINUOUS_DQS = FALSE) and RX_GATING = ENABLE, bitslip is not needed. For all other cases, bitslip is needed for word alignment.