Register Interface Unit

Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)
Document ID
AM010
Release Date
2024-03-18
Revision
1.5 English

The register interface unit (RIU) is a set of 74 read/write, 16-bit registers that dynamically provides access to XPHY features. Each XPHY nibble has its own RIU, allowing all nine nibbles in a bank to be accessed simultaneously.

Important: When writing to the RIU, always preserve the value of any bits marked as RESERVED.
Important: Any mention of crse with respect to input, output, or quarter delays should only be thought of as part of an arbitrary bus name and does not indicate functionality. The coarse delay block is separate from the other delay blocks.
Important: RIU writes by BISC take precedence over RIU writes from the PL. If an RIU write from the PL collides with one from BISC, RIU_RD_VALID will deassert and the PL RIU write from the cycle before RIU_RD_VALID deasserted will be stored. After BISC finishes its write(s), RIU_RD_VALID will assert and the stored PL RIU write will be executed. Any writes from the PL while RIU_RD_VALID is Low will be discarded.

To read from the RIU, assert RIU_NIBBLE_SEL as shown in the following waveform.

Figure 1. RIU Read Operation

To write to the RIU, assert RIU_NIBBLE_SEL and RIU_WR_EN as shown in the following waveform. Notice the latency difference between reading (1 cycle) and writing (2 cycles). RIU_RD_VALID also applies to RIU writes from the PL. RIU_RD_VALID being High is necessary for the writes to be successful.

Figure 2. RIU Write Operation
Table 1. Register Description (NIBBLE_CTRL0)
NIBBLE_CTRL0 ADDR: 0x00
Bits Access Type Reset Value Name Description
[0] rw EN_OTHER_PCLK en_other_pclk See the description of the EN_OTHER_PCLK attribute in Attributes
[1] rw EN_OTHER_NCLK en_other_nclk See the description of the EN_OTHER_NCLK attribute in Attributes
[2] rw INV_RXCLK inv_rxclk See the description of the INV_RXCLK attribute in Attributes
[3] rw SERIAL_MODE serial_mode See the description of the SERIAL_MODE attribute in Attributes. If the RIU (as opposed to the SERIAL_MODE attribute) is used to set this bit, BISC clears this bit as part of calibration. Set this bit again after BISC completes.
[4] rw TX_GATING tx_gating See the description of the TX_GATING attribute in Attributes
[5] rw RX_GATING rx_gating See the description of the RX_GATING attribute in Attributes
[6] rw CONTINUOUS_DQS rxgating_extend See the description of the CONTINUOUS_DQS attribute in Attributes
[15:7] RESERVED Reserved
Table 2. Register Description (NIBBLE_CTRL1)
NIBBLE_CTRL1 ADDR: 0x01
Bits Access Type Reset Value Name Description
[0] rw RX_CLK_PHASE_P rx_clk_phase_p See the description of the RX_CLK_PHASE_P attribute in Attributes
[1] rw RX_CLK_PHASE_N rx_clk_phase_n See the description of the RX_CLK_PHASE_N attribute in Attributes
[2] rw TX_OUTPUT_PHASE_90_0 tx_out_phase_90_0 See the description of the TX_OUTPUT_PHASE_90_<0-5> attribute in Attributes
[3] rw TX_OUTPUT_PHASE_90_1 tx_out_phase_90_1 See the description of the TX_OUTPUT_PHASE_90_<0-5> attribute in Attributes
[4] rw TX_OUTPUT_PHASE_90_2 tx_out_phase_90_2 See the description of the TX_OUTPUT_PHASE_90_<0-5> attribute in Attributes
[5] rw TX_OUTPUT_PHASE_90_3 tx_out_phase_90_3 See the description of the TX_OUTPUT_PHASE_90_<0-5> attribute in Attributes
[6] rw TX_OUTPUT_PHASE_90_4 tx_out_phase_90_4 See the description of the TX_OUTPUT_PHASE_90_x attribute in Attributes
[7] rw TX_OUTPUT_PHASE_90_5 tx_out_phase_90_5 See the description of the TX_OUTPUT_PHASE_90_<0-5> attribute in Attributes
[8] RESERVED Reserved
[9] rw TX_OUTPUT_PHASE_90_TRI tx_out_phase_90_tri See the description of the TX_OUTPUT_PHASE_90_TRI attribute in Attributes
[15:10] RESERVED Reserved
Table 3. Register Description (CALIB_CTRL)
CALIB_CTRL ADDR: 0x02
Bits Access Type Reset Value Name Description
[0] rw SELF_CALIBRATE self_calibrate See the description of the SELF_CALIBRATE attribute in Attributes.
[1] rw DIS_IDLY_VT_TRACK dis_vttrack_ibit See the description of the DIS_IDLY_VT_TRACK attribute in Attributes.
[2] rw DIS_ODLY_VT_TRACK dis_vttrack_obit See the description of the DIS_ODLY_VT_TRACK attribute in Attributes.
[10:3] RESERVED Reserved.
[11] ro 0x0 fixdly_rdy When 1, fixdly_rdy indicates that calibration is complete (equivalent to DLY_RDY asserting on the XPHY). If 0, calibration is not complete yet. See Ports for a description of DLY_RDY.
[12] ro 0x0 phy_rdy The behavior of phy_rdy matches that of the PHY_RDY port. See the description of the PHY_RDY port in Ports for more information.
[13] RESERVED Reserved.
[14] rw DIS_QDLY_VT_TRACK dis_vttrack_qdly See the description of the DIS_QDLY_VT_TRACK attribute in Ports.
[15] ro 0x0 pause_rdy Indicates that BISC is paused. See WL_TRAIN.bisc_pause for more information on pausing BISC.
Table 4. Register Description (BS_RESET_CTRL)
BS_RESET_CTRL ADDR: 0x03
Bits Access Type Reset Value Name Description
[0] rw 0x0 clr_gate Toggling this bit clears the strobe path gating logic.
[1] rw 0x0 bs_reset NIBBLESLICE reset. When set, NIBBLESLICEs not masked by BS_RST_MASK.bs_reset_mask are reset. Prior to asserting this bit, set PHY_WREN and PHY_RDEN to 0 if they are not already tied off to 0, regardless of the value of the TX_GATING or RX_GATING attributes. The bs_reset must be asserted for a minimum amount of time, defined by its data width (the TX_DATA_WIDTH and RX_DATA_WIDTH attributes):
  • For data width of 8: 1 CTRL_CLK cycle + 72 PLL_CLK cycles
  • For data width of 4: 1 CTRL_CLK cycle + 40 PLL_CLK cycles
  • For data width of 2: 1 CTRL_CLK cycle + 24 PLL_CLK cycles

While bs_reset is asserted, the TX IOBs of NIBBLESLICEs not masked by BS_RST_MASK.bs_reset_mask are set to the value of the their associated TX_INIT_# attribute. After bs_reset is deasserted, data can be transmitted immediately. For receivers, however, the first FIFO_EMPTY deassertion should be used to know when receiving valid data. Also, after the deassertion of bs_reset, PHY_RDEN and PHY_WREN can now be changed from 0.
[2] rw 0x0 bs_reset_tri Tristate NIBBLESLICE reset. When asserted, the tristate NIBBLESLICE is set to the value of the TX_INIT_TRI attribute if not masked by BS_RST_MASK.bs_reset_tri_mask. bs_reset_tri must be asserted for a minimum amount of time, defined by the interface's data width (the TX_DATA_WIDTH and RX_DATA_WIDTH attributes):
  • For data width of 8: 1 CTRL_CLK cycle + 72 PLL_CLK cycles
  • For data width of 4: 1 CTRL_CLK cycle + 40 PLL_CLK cycles
  • For data width of 2: 1 CTRL_CLK cycle + 24 PLL_CLK cycles

Set PHY_WREN = 0 when issuing this reset.
[15:3] RESERVED Reserved.
Table 5. Register Description (PQTR)
PQTR ADDR: 0x07
Bits Access Type Reset Value Name Description
[8:0] rw 0x0 pqtr_dly P-clk quarter delay. See pqtr_crse for the different ways to update pqtr_dly.
[12:9] RESERVED Reserved.
[13] wo 0x0 pqtr_crse Along with pqtr_dec and pqtr_inc, determines how pqtr_dly will change.
  • {pqtr_inc, pqtr_dec, pqtr_crse}:
  • 000, 001, 110, 111: This allows for pqtr_dly to be written to directly.
  • 100: Increment pqtr_dly by one tap. Wrap around to 0x0 will happen when this increment occurs at pqtr_dly = 0x1ff.
  • 010: Decrement pqtr_dly by one tap. Wrap around to 0x1ff will happen when this decrement occurs at pqtr_dly = 0x0.
  • 101: Increment pqtr_dly by INCDEC_CRSE.incdec_crse. When pqtr_dly is close to 0x1ff, this increment may wrap it around to above 0x0.
  • 011: Decrement pqtr_dly by INCDEC_CRSE.incdec_crse. When pqtr_dly is close to 0x0, this decrement may wrap it around to below 0x1ff.

To prevent misalignment, if the update is by more than one tap, wait five CTRL_CLK + four strobe/capture clock cycles, then apply a bs_reset on all NIBBLESLICEs affected by the quarter delay line update (even if it's through inter-nibble or inter-byte clocking) after the update.
[14] wo 0x0 pqtr_dec P-clk quarter delay decrement. See the description for pqtr_crse.
[15] wo 0x0 pqtr_inc P-clk quarter delay increment. See the description for pqtr_crse.
Table 6. Register Description (NQTR)
NQTR ADDR: 0x08
Bits Access Type Reset Value Name Description
[8:0] rw 0x0 nqtr_dly N-clk quarter delay. See nqtr_crse for the different ways to update nqtr_dly.
[12:9] RESERVED Reserved.
[13] wo 0x0 nqtr_crse Along with nqtr_dec and nqtr_inc, determines how nqtr_dly will change.
  • {nqtr_inc, nqtr_dec, nqtr_crse}:
  • 000, 001, 110, 111: This allows for nqtr_dly to be written to directly.
  • 100: Increment nqtr_dly by one tap. Wrap around to 0x0 will happen when this increment occurs at nqtr_dly = 0x1ff.
  • 010: Decrement nqtr_dly by one tap. Wrap around to 0x1ff will happen when this decrement occurs at nqtr_dly = 0x0.
  • 101: Increment nqtr_dly by INCDEC_CRSE.incdec_crse. When nqtr_dly is close to 0x1ff, this increment may wrap it around to above 0x0.
  • 011: Decrement nqtr_dly by INCDEC_CRSE.incdec_crse. When nqtr_dly is close to 0x0, this decrement may wrap it around to below 0x1ff.

To prevent misalignment, if the update is by more than one tap, wait five CTRL_CLK + four strobe/capture clock cycles, then apply a bs_reset on all NIBBLESLICEs affected by the quarter delay line update (even if it's through inter-nibble or inter-byte clocking) after the update.
[14] wo 0x0 nqtr_dec N-clk quarter delay decrement. See the description for nqtr_crse.
[15] wo 0x0 nqtr_inc N-clk quarter delay increment. See the description for nqtr_crse.
Table 7. Register Description (TRISTATE_ODLY)
TRISTATE_ODLY ADDR: 0x0a
Bits Access Type Reset Value Name Description
[8:0] rw 0x0 tristate_dly Tristate NIBBLESLICE delay value. See tristate_crse for the different ways to update tristate_dly.
[12:9] RESERVED Reserved
[13] wo 0x0 tristate_crse Along with tristate_dec and tristate_inc, determines how tristate_dly will change.
  • {tristate_inc, tristate_dec, tristate_crse}:
  • 000, 001, 110, 111: This allows for tristate_dly to be written to.
  • 100: Increment tristate_dly by one tap. Wrap around to 0x0 will happen when this increment occurs at tristate_dly = 0x1ff
  • 010: Decrement tristate_dly by one tap. Wrap around to 0x1ff will happen when this decrement occurs at tristate_dly = 0x0
  • 101: Increment tristate_dly by INCDEC_CRSE.incdec_crse. When tristate_dly is close to 0x1ff, this increment may wrap it around to above 0x0
  • 011: Decrement tristate_dly by INCDEC_CRSE.incdec_crse. When tristate_dly is close to 0x0, this decrement may wrap it around to below 0x1ff
[14] wo 0x0 tristate_dec Tristate NIBBLESLICE delay decrement. See the description for tristate_crse.
[15] wo 0x0 tristate_inc Tristate NIBBLESLICE delay increment. See the description for tristate_crse.
Table 8. Register Description (ODLY0)
ODLY0 ADDR: 0x0b
Bits Access Type Reset Value Name Description
[8:0] rw 0x0 odly0_dly NIBBLESLICE[0] output delay value.

Reading odly0_dly returns the output delay value in NIBBLESLICE[0], similar to reading CNTVALUEOUT[8:0] from the PL. See odly0_crse for the different ways to update odly0_dly.
[12:9] RESERVED Reserved
[13] wo 0x0 odly0_crse Along with odly0_dec and odly0_inc, determines how odly0_dly will change.
  • {odly0_crse, odly0_dec, odly0_inc}:
  • 000, 011, 100, 111: This allows for odly0_dly to be written to directly, similar to loading a delay from the PL to CNTVALUEIN[8:0].
  • 001: Increment odly0_dly by one tap. Wrap around to 0x0 will happen when this increment occurs at odly0_dly = 0x1ff
  • 010: Decrement odly0_dly by one tap. Wrap around to 0x1ff will happen when this decrement occurs at odly0_dly = 0x0
  • 101: Increment odly0_dly by INCDEC_CRSE.incdec_crse. When odly0_dly is close to 0x1ff, this increment may wrap it around to above 0x0
  • 110: Decrement odly0_dly by INCDEC_CRSE.incdec_crse. When odly0_dly is close to 0x0, this decrement may wrap it around to below 0x1ff
[14] wo 0x0 odly0_dec NIBBLESLICE[0] output delay decrement. See the description for odly0_crse.
[15] wo 0x0 odly0_inc NIBBLESLICE[0] output delay increment. See the description for odly0_crse.
Table 9. Register Description (ODLY1)
ODLY1 ADDR: 0x0c
Bits Access Type Reset Value Name Description
[8:0] rw 0x0 odly1_dly NIBBLESLICE[1] output delay value.

Reading odly1_dly returns the output delay value in NIBBLESLICE[1], similar to reading CNTVALUEOUT[17:9] from the PL. See odly1_crse for the different ways to update odly1_dly.
[12:9] RESERVED Reserved
[13] wo 0x0 odly1_crse Along with odly1_dec and odly1_inc, determines how odly1_dly will change.
  • {odly1_crse, odly1_dec, odly1_inc}:
  • 000, 011, 100, 111: This allows for odly1_dly to be written to directly, similar to loading a delay from the PL to CNTVALUEIN[17:9].
  • 001: Increment odly1_dly by one tap. Wrap around to 0x0 will happen when this increment occurs at odly1_dly = 0x1ff
  • 010: Decrement odly1_dly by one tap. Wrap around to 0x1ff will happen when this decrement occurs at odly1_dly = 0x0
  • 101: Increment odly1_dly by INCDEC_CRSE.incdec_crse. When odly1_dly is close to 0x1ff, this increment may wrap it around to above 0x0
  • 110: Decrement odly1_dly by INCDEC_CRSE.incdec_crse. When odly1_dly is close to 0x0, this decrement may wrap it around to below 0x1ff
[14] wo 0x0 odly1_dec NIBBLESLICE[1] output delay decrement. See the description for odly1_crse.
[15] wo 0x0 odly1_inc NIBBLESLICE[1] output delay increment. See the description for odly1_crse.
Table 10. Register Description (ODLY2)
ODLY2 ADDR: 0x0d
Bits Access Type Reset Value Name Description
[8:0] rw 0x0 odly2_dly NIBBLESLICE[2] output delay value.

Reading odly2_dly returns the output delay value in NIBBLESLICE[2], similar to reading CNTVALUEOUT[26:18] from the PL. See odly2_crse for the different ways to update odly2_dly.
[12:9] RESERVED Reserved
[13] wo 0x0 odly2_crse Along with odly2_dec and odly2_inc, determines how odly2_dly will change.
  • {odly2_crse, odly2_dec, odly2_inc}:
  • 000, 011, 100, 111: This allows for odly2_dly to be written to directly, similar to loading a delay from the PL to CNTVALUEIN[26:18].
  • 001: Increment odly2_dly by one tap. Wrap around to 0x0 will happen when this increment occurs at odly2_dly = 0x1ff
  • 010: Decrement odly2_dly by one tap. Wrap around to 0x1ff will happen when this decrement occurs at odly2_dly = 0x0
  • 101: Increment odly2_dly by INCDEC_CRSE.incdec_crse. When odly2_dly is close to 0x1ff, this increment may wrap it around to above 0x0
  • 110: Decrement odly2_dly by INCDEC_CRSE.incdec_crse. When odly2_dly is close to 0x0, this decrement may wrap it around to below 0x1ff
[14] wo 0x0 odly2_dec NIBBLESLICE[2] output delay decrement. See the description for odly2_crse.
[15] wo 0x0 odly2_inc NIBBLESLICE[2] output delay increment. See the description for odly2_crse.
Table 11. Register Description (ODLY3)
ODLY3 ADDR: 0x0e
Bits Access Type Reset Value Name Description
[8:0] rw 0x0 odly3_dly NIBBLESLICE[3] output delay value.

Reading odly3_dly returns the output delay value in NIBBLESLICE[3], similar to reading CNTVALUEOUT[35:27] from the PL. See odly3_crse for the different ways to update odly3_dly.
[12:9] RESERVED Reserved
[13] wo 0x0 odly3_crse Along with odly3_dec and odly3_inc, determines how odly3_dly will change.
  • {odly3_crse, odly3_dec, odly3_inc}:
  • 000, 011, 100, 111: This allows for odly3_dly to be written to directly, similar to loading a delay from the PL to CNTVALUEIN[35:27].
  • 001: Increment odly3_dly by one tap. Wrap around to 0x0 will happen when this increment occurs at odly3_dly = 0x1ff
  • 010: Decrement odly3_dly by one tap. Wrap around to 0x1ff will happen when this decrement occurs at odly3_dly = 0x0
  • 101: Increment odly3_dly by INCDEC_CRSE.incdec_crse. When odly3_dly is close to 0x1ff, this increment may wrap it around to above 0x0
  • 110: Decrement odly3_dly by INCDEC_CRSE.incdec_crse. When odly3_dly is close to 0x0, this decrement may wrap it around to below 0x1ff
[14] wo 0x0 odly3_dec NIBBLESLICE[3] output delay decrement. See the description for odly3_crse.
[15] wo 0x0 odly3_inc NIBBLESLICE[3] output delay increment. See the description for odly3_crse.
Table 12. Register Description (ODLY4)
ODLY4 ADDR: 0x0f
Bits Access Type Reset Value Name Description
[8:0] rw 0x0 odly4_dly NIBBLESLICE[4] output delay value.

Reading odly4_dly returns the output delay value in NIBBLESLICE[4], similar to reading CNTVALUEOUT[44:36] from the PL. See odly4_crse for the different ways to update odly4_dly.
[12:9] RESERVED Reserved
[13] wo 0x0 odly4_crse Along with odly4_dec and odly4_inc, determines how odly4_dly will change.
  • {odly4_crse, odly4_dec, odly4_inc}:
  • 000, 011, 100, 111: This allows for odly4_dly to be written to directly, similar to loading a delay from the PL to CNTVALUEIN[44:36].
  • 001: Increment odly4_dly by one tap. Wrap around to 0x0 will happen when this increment occurs at odly4_dly = 0x1ff
  • 010: Decrement odly4_dly by one tap. Wrap around to 0x1ff will happen when this decrement occurs at odly4_dly = 0x0
  • 101: Increment odly4_dly by INCDEC_CRSE.incdec_crse. When odly4_dly is close to 0x1ff, this increment may wrap it around to above 0x0
  • 110: Decrement odly4_dly by INCDEC_CRSE.incdec_crse. When odly4_dly is close to 0x0, this decrement may wrap it around to below 0x1ff
[14] wo 0x0 odly4_dec NIBBLESLICE[4] output delay decrement. See the description for odly4_crse.
[15] wo 0x0 odly4_inc NIBBLESLICE[4] output delay increment. See the description for odly4_crse.
Table 13. Register Description (ODLY5)
ODLY5 ADDR: 0x10
Bits Access Type Reset Value Name Description
[8:0] rw 0x0 odly5_dly NIBBLESLICE[5] output delay value.

Reading odly5_dly returns the output delay value in NIBBLESLICE[5], similar to reading CNTVALUEOUT[53:45] from the PL. See odly5_crse for the different ways to update odly5_dly.
[12:9] RESERVED Reserved
[13] wo 0x0 odly5_crse Along with odly5_dec and odly5_inc, determines how odly5_dly will change.
  • {odly5_crse, odly5_dec, odly5_inc}:
  • 000, 011, 100, 111: This allows for odly5_dly to be written to directly, similar to loading a delay from the PL to CNTVALUEIN[53:45].
  • 001: Increment odly5_dly by one tap. Wrap around to 0x0 will happen when this increment occurs at odly5_dly = 0x1ff
  • 010: Decrement odly5_dly by one tap. Wrap around to 0x1ff will happen when this decrement occurs at odly5_dly = 0x0
  • 101: Increment odly5_dly by INCDEC_CRSE.incdec_crse. When odly5_dly is close to 0x1ff, this increment may wrap it around to above 0x0
  • 110: Decrement odly5_dly by INCDEC_CRSE.incdec_crse. When odly5_dly is close to 0x0, this decrement may wrap it around to below 0x1ff
[14] wo 0x0 odly5_dec NIBBLESLICE[5] output delay decrement. See the description for odly5_crse.
[15] wo 0x0 odly5_inc NIBBLESLICE[5] output delay increment. See the description for odly5_crse.
Table 14. Register Description (BS_RST_MASK)
BS_RST_MASK ADDR: 0x11
Bits Access Type Reset Value Name Description
[5:0] rw 0x0 bs_reset_mask NIBBLESLICE reset mask. When bit x is set, the corresponding NIBBLESLICE[x] will not get reset when a 1 is written to BS_RESET_CTRL.bs_reset.
[6] rw 0x0 bs_reset_tri_mask Tristate NIBBLESLICE reset mask. When set, the tristate NIBBLESLICE will not get reset when a 1 is written to BS_RESET_CTRL.bs_reset_tri.
[15:7] RESERVED Reserved
Table 15. Register Description (IDLY0)
IDLY0 ADDR: 0x12
Bits Access Type Reset Value Name Description
[8:0] rw 0x0 idly0_dly NIBBLESLICE[0] input delay value. idly0_dly does include align_delay, but writes or updates to idly0_dly do not change align_delay.

Reading idly0_dly returns the input delay value in NIBBLESLICE[0], similar to reading CNTVALUEOUT[8:0] from the PL. See idly0_crse for the different ways to update idly0_dly.
[12:9] RESERVED Reserved
[13] wo 0x0 idly0_crse Along with idly0_dec and idly0_inc, determines how idly0_dly will change.
  • {idly0_crse, idly0_dec, idly0_inc}:
  • 000, 011, 100, 111: This allows for idly0_dly to be written to directly, similar to loading a delay from the PL to CNTVALUEIN[8:0].
  • 001: Increment idly0_dly by one tap. Wrap around to 0x0 will happen when this increment occurs at idly0_dly = 0x1ff
  • 010: Decrement idly0_dly by one tap. Wrap around to 0x1ff will happen when this decrement occurs at idly0_dly = 0x0
  • 101: Increment idly0_dly by INCDEC_CRSE.incdec_crse. When idly0_dly is close to 0x1ff, this increment may wrap it around to above 0x0
  • 110: Decrement idly0_dly by INCDEC_CRSE.incdec_crse. When idly0_dly is close to 0x0, this decrement may wrap it around to below 0x1ff
[14] wo 0x0 idly0_dec NIBBLESLICE[0] input delay decrement. See the description for idly0_crse.
[15] wo 0x0 idly0_inc NIBBLESLICE[0] input delay increment. See the description for idly0_crse.
Table 16. Register Description (IDLY1)
IDLY1 ADDR: 0x13
Bits Access Type Reset Value Name Description
[8:0] rw 0x0 idly1_dly NIBBLESLICE[1] input delay value. idly1_dly does include align_delay, but writes or updates to idly1_dly do not change align_delay.

Reading idly1_dly returns the input delay value in NIBBLESLICE[1], similar to reading CNTVALUEOUT[17:9] from the PL. See idly1_crse for the different ways to update idly1_dly.
[12:9] RESERVED Reserved
[13] wo 0x0 idly1_crse Along with idly1_dec and idly1_inc, determines how idly1_dly will change.
  • {idly1_crse, idly1_dec, idly1_inc}:
  • 000, 011, 100, 111: This allows for idly1_dly to be written to directly, similar to loading a delay from the PL to CNTVALUEIN[17:9].
  • 001: Increment idly1_dly by one tap. Wrap around to 0x0 will happen when this increment occurs at idly1_dly = 0x1ff
  • 010: Decrement idly1_dly by one tap. Wrap around to 0x1ff will happen when this decrement occurs at idly1_dly = 0x0
  • 101: Increment idly1_dly by INCDEC_CRSE.incdec_crse. When idly1_dly is close to 0x1ff, this increment may wrap it around to above 0x0
  • 110: Decrement idly1_dly by INCDEC_CRSE.incdec_crse. When idly1_dly is close to 0x0, this decrement may wrap it around to below 0x1ff
[14] wo 0x0 idly1_dec NIBBLESLICE[1] input delay decrement. See the description for idly1_crse.
[15] wo 0x0 idly1_inc NIBBLESLICE[1] input delay increment. See the description for idly1_crse.
Table 17. Register Description (IDLY2)
IDLY2 ADDR: 0x14
Bits Access Type Reset Value Name Description
[8:0] rw 0x0 idly2_dly NIBBLESLICE[2] input delay value. idly2_dly does include align_delay, but writes or updates to idly2_dly do not change align_delay.

Reading idly2_dly returns the input delay value in NIBBLESLICE[2], similar to reading CNTVALUEOUT[26:18] from the PL. See idly2_crse for the different ways to update idly2_dly.
[12:9] RESERVED Reserved
[13] wo 0x0 idly2_crse Along with idly2_dec and idly2_inc, determines how idly2_dly will change.
  • {idly2_crse, idly2_dec, idly2_inc}:
  • 000, 011, 100, 111: This allows for idly2_dly to be written to directly, similar to loading a delay from the PL to CNTVALUEIN[26:18].
  • 001: Increment idly2_dly by one tap. Wrap around to 0x0 will happen when this increment occurs at idly2_dly = 0x1ff
  • 010: Decrement idly2_dly by one tap. Wrap around to 0x1ff will happen when this decrement occurs at idly2_dly = 0x0
  • 101: Increment idly2_dly by INCDEC_CRSE.incdec_crse. When idly2_dly is close to 0x1ff, this increment may wrap it around to above 0x0
  • 110: Decrement idly2_dly by INCDEC_CRSE.incdec_crse. When idly2_dly is close to 0x0, this decrement may wrap it around to below 0x1ff
[14] wo 0x0 idly2_dec NIBBLESLICE[2] input delay decrement. See the description for idly2_crse.
[15] wo 0x0 idly2_inc NIBBLESLICE[2] input delay increment. See the description for idly2_crse.
Table 18. Register Description (IDLY3)
IDLY3 ADDR: 0x15
Bits Access Type Reset Value Name Description
[8:0] rw 0x0 idly3_dly NIBBLESLICE[3] input delay value. idly3_dly does include align_delay, but writes or updates to idly3_dly do not change align_delay.

Reading idly3_dly returns the input delay value in NIBBLESLICE[3], similar to reading CNTVALUEOUT[35:27] from the PL. See idly3_crse for the different ways to update idly3_dly.
[12:9] RESERVED Reserved
[13] wo 0x0 idly3_crse Along with idly3_dec and idly3_inc, determines how idly3_dly will change.
  • {idly3_crse, idly3_dec, idly3_inc}:
  • 000, 011, 100, 111: This allows for idly3_dly to be written to directly, similar to loading a delay from the PL to CNTVALUEIN[35:27].
  • 001: Increment idly3_dly by one tap. Wrap around to 0x0 will happen when this increment occurs at idly3_dly = 0x1ff
  • 010: Decrement idly3_dly by one tap. Wrap around to 0x1ff will happen when this decrement occurs at idly3_dly = 0x0
  • 101: Increment idly3_dly by INCDEC_CRSE.incdec_crse. When idly3_dly is close to 0x1ff, this increment may wrap it around to above 0x0
  • 110: Decrement idly3_dly by INCDEC_CRSE.incdec_crse. When idly3_dly is close to 0x0, this decrement may wrap it around to below 0x1ff
[14] wo 0x0 idly3_dec NIBBLESLICE[3] input delay decrement. See the description for idly3_crse.
[15] wo 0x0 idly3_inc NIBBLESLICE[3] input delay increment. See the description for idly3_crse.
Table 19. Register Description (IDLY4)
IDLY4 ADDR: 0x16
Bits Access Type Reset Value Name Description
[8:0] rw 0x0 idly4_dly NIBBLESLICE[4] input delay value. idly4_dly does include align_delay, but writes or updates to idly4_dly do not change align_delay.

Reading idly4_dly returns the input delay value in NIBBLESLICE[4], similar to reading CNTVALUEOUT[44:36] from the PL. See idly4_crse for the different ways to update idly4_dly.
[12:9] RESERVED Reserved
[13] wo 0x0 idly4_crse Along with idly4_dec and idly4_inc, determines how idly4_dly will change.
  • {idly4_crse, idly4_dec, idly4_inc}:
  • 000, 011, 100, 111: This allows for idly4_dly to be written to directly, similar to loading a delay from the PL to CNTVALUEIN[44:36].
  • 001: Increment idly4_dly by one tap. Wrap around to 0x0 will happen when this increment occurs at idly4_dly = 0x1ff
  • 010: Decrement idly4_dly by one tap. Wrap around to 0x1ff will happen when this decrement occurs at idly4_dly = 0x0
  • 101: Increment idly4_dly by INCDEC_CRSE.incdec_crse. When idly4_dly is close to 0x1ff, this increment may wrap it around to above 0x0
  • 110: Decrement idly4_dly by INCDEC_CRSE.incdec_crse. When idly4_dly is close to 0x0, this decrement may wrap it around to below 0x1ff
[14] wo 0x0 idly4_dec NIBBLESLICE[4] input delay decrement. See the description for idly4_crse.
[15] wo 0x0 idly4_inc NIBBLESLICE[4] input delay increment. See the description for idly4_crse.
Table 20. Register Description (IDLY5)
IDLY5 ADDR: 0x17
Bits Access Type Reset Value Name Description
[8:0] rw 0x0 idly5_dly NIBBLESLICE[5] input delay value. idly5_dly does include align_delay, but writes or updates to idly5_dly do not change align_delay.

Reading idly5_dly returns the input delay value in NIBBLESLICE[5], similar to reading CNTVALUEOUT[53:45] from the PL. See idly5_crse for the different ways to update idly5_dly.
[12:9] RESERVED Reserved
[13] wo 0x0 idly5_crse Along with idly5_dec and idly5_inc, determines how idly5_dly will change.
  • {idly5_crse, idly5_dec, idly5_inc}:
  • 000, 011, 100, 111: This allows for idly5_dly to be written to directly, similar to loading a delay from the PL to CNTVALUEIN[53:45].
  • 001: Increment idly5_dly by one tap. Wrap around to 0x0 will happen when this increment occurs at idly5_dly = 0x1ff
  • 010: Decrement idly5_dly by one tap. Wrap around to 0x1ff will happen when this decrement occurs at idly5_dly = 0x0
  • 101: Increment idly5_dly by INCDEC_CRSE.incdec_crse. When idly5_dly is close to 0x1ff, this increment may wrap it around to above 0x0
  • 110: Decrement idly5_dly by INCDEC_CRSE.incdec_crse. When idly5_dly is close to 0x0, this decrement may wrap it around to below 0x1ff
[14] wo 0x0 idly5_dec NIBBLESLICE[5] input delay decrement. See the description for idly5_crse.
[15] wo 0x0 idly5_inc NIBBLESLICE[5] input delay increment. See the description for idly5_crse.
Table 21. Register Description (CRSE_DLY)
CRSE_DLY ADDR: 0x18
Bits Access Type Reset Value Name Description
[4:0] rw 0x0 crse_dly Coarse delay
[13:5] RESERVED Reserved
[14] wo 0x0 crse_dec Along with crse_inc, determines how crse_dly will change.
  • {crse_inc, crse_dec}:
  • 00, 11: This allows for crse_dly to be written to directly.
  • 10: Increment crse_dly by one tap. Wrap around to 0x0 will happen when this increment occurs at crse_dly = 0x1f
  • 01: Decrement by one tap. Wrap around to 0x1ff will happen when this decrement occurs at 0x0

To prevent misalignment, wait five CTRL_CLK + four strobe/capture clock cycles, then apply a bs_reset on all NIBBLESLICEs affected by the coarse delay line update (even if it is through inter-nibble or inter-byte clocking) after the update.
[15] wo 0x0 crse_inc Coarse delay increment. See the description for crse_dec.
Table 22. Register Description (WL_TRAIN)
WL_TRAIN ADDR: 0x2b
Bits Access Type Reset Value Name Description
[0] RESERVED Reserved
[1] rw 0x0 en_vtc This operates in the same way as the EN_VTC port. See Controlling Built-in Self-Calibration for more details on VTC.
[6:2] RESERVED Reserved
[7] rw 0x0 bisc_pause When set, pauses BISC
[15:8] RESERVED Reserved
Table 23. Register Description (RD_IDLE_COUNT)
RD_IDLE_COUNT ADDR: 0x34
Bits Access Type Reset Value Name Description
[5:0] rw 0x10 rd_idle_count The number of cycles with frequency equal to PLL_CLK/RX_DATA_WIDTH that must occur after the deassertion of PHY_RDEN (following a read burst) before ODT is disabled. See Controlling IBUF_DISABLE and DYN_DCI for more information.
[15:7] RESERVED Reserved
Table 24. Register Description (RL_DLY_QTR)
RL_DLY_QTR ADDR: 0x36
Bits Access Type Reset Value Name Description
[8:0] rw 0x0 rl_dly_qtr Read quarter cycle delay. Used to know the number of taps equivalent to 90° to detect quarter cycle rollover.
[15:9] RESERVED Reserved
Table 25. Register Description (INCDEC_CRSE)
INCDEC_CRSE ADDR: 0x3b
Bits Access Type Reset Value Name Description
[7:0] rw 0x08 incdec_crse Represents the number of taps used for certain delay line updates (input delays, output delays, tristate output delays, and quarter (QTR) delays) when updated through the RIU.
[15:8] RESERVED Reserved
Table 26. Register Description (NIBBLE_CTRL2)
NIBBLE_CTRL2 ADDR: 0x3e
Bits Access Type Reset Value Name Description
[0] rw 0x0 odt_0 Contributes to NIBBLESLICE[0]'s on-die termination (ODT) control. See Controlling IBUF_DISABLE and DYN_DCI for more information.
[1] rw 0x0 odt_1 Contributes to NIBBLESLICE[1]'s ODT control. See Controlling IBUF_DISABLE and DYN_DCI for more information.
[2] rw 0x0 odt_2 Contributes to NIBBLESLICE[2]'s ODT control. See Controlling IBUF_DISABLE and DYN_DCI for more information.
[3] rw 0x0 odt_3 Contributes to NIBBLESLICE[3]'s ODT control. See Controlling IBUF_DISABLE and DYN_DCI for more information.
[4] rw 0x0 odt_4 Contributes to NIBBLESLICE[4]'s ODT control. See Controlling IBUF_DISABLE and DYN_DCI for more information.
[5] rw 0x0 odt_5 Contributes to NIBBLESLICE[5]'s ODT control. See Controlling IBUF_DISABLE and DYN_DCI for more information.
[9:6] RESERVED Reserved
[10] rw CRSE_DLY_EN crse_dly_enable See the description of the CRSE_DLY_EN attribute in Attributes.
[13:11] rw DQS_MODE dqs_mode See the description of the DQS_MODE attribute in Attributes.
[15:14] RESERVED Reserved
Table 27. Register Description (TXRX_LOOPBACK)
TXRX_LOOPBACK ADDR: 0x3f
Bits Access Type Reset Value Name Description
[5:0] rw {TXRX_LOOPBACK_5, TXRX_LOOPBACK_4, TXRX_LOOPBACK_3, TXRX_LOOPBACK_2, TXRX_LOOPBACK_1, TXRX_LOOPBACK_0} txrx_loopback See the description of the TXRX_LOOPBACK_<0-5> attribute in Attributes.
[15:6] RESERVED Reserved
Table 28. Register Description (ODELAY_BYPASS)
ODELAY_BYPASS ADDR: 0x40
Bits Access Type Reset Value Name Description
[5:0] rw 0x0 odelay_bypass When bit x is set, the output delay of NIBBLESLICE[x] is bypassed
[15:6] RESERVED Reserved