MIPI-DPHY Input Buffer Primitive

Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)
Document ID
AM010
Release Date
2024-03-18
Revision
1.5 English
Figure 1. MIPI-DPHY Input Buffer Primitive

Table 1. IBUFDS_DPHY Attributes
Attribute Values Description
IOSTANDARD MIPI_DPHY Assigns an I/O standard to the element.
DIFF_TERM TRUE, FALSE Turns the built-in differential termination on (TRUE) or off (FALSE).
Table 2. IBUFDS_DPHY Ports
Port I/O Description
HSRX_O Output Inputs to the interconnect logic from the HS receiver.
LPRX_O_P Output Inputs to the interconnect logic from the low-power (LP) receiver.
LPRX_O_N Output Inputs to the interconnect logic from the low-power (LP) receiver.
I Input Input port connection. Connect directly to top-level P-side port in the design.
IB Input Input port connection. Connect directly to top-level N-side port in the design.
HSRX_DISABLE Input The HSRX_DISABLE port is used to enable or disable the MIPI D-PHY high-speed (HS) receiver.
LPRX_DISABLE Input The LPRX_DISABLE port is used to enable or disable the low-power (LP) receiver.