Revision History - AM010

Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)
Document ID
AM010
Release Date
2025-05-22
Revision
1.7 English

The following table shows the revision history for this document.

Section Revision Summary
05/22/2025 Version 1.7
General updates Added X5 I/O throughout.
XPIO Features Added 1.1V bank voltage standard.
X5IO Features Removed DFE from receive equalization bullet.
SelectIO Resources Architecture Updated lower end of XPIO bank support voltage level to 1.0V.
XP IOB
  • Added supported bank voltage of 1.1V.
  • Added output drive strength of 2 mA and 6 mA.
X5IO IOB Added output drive strength of 2 mA and 6 mA.
X5IO PHY
  • Added LPDDR5X.
  • Removed DDR4 and LPDDR4.
Clocking Added important note about pin name information.
Table 29 Added table.
Uncalibrated IOB Delay Added sentence about cascading to first paragraph.
Corner Banks, DDRMC_ONLY, and PL Only Pins Updated to clarify DDRMC_ONLY.
Figure 2 Added figure.
Table 1 Updated required INTERNAL_VREF for LVSTL06_12 to 0.150V.
Figure 1 Added IOBUF_DCIEN.
XP IOB Internal VREF Added XDC commands.
Corner Banks Updated to clarify DDRMC_ONLY.
HD IOL Features Added sentence about cascading to first paragraph.
Corner Banks, DDRMC_ONLY, PL Only Banks, and Shared NMU Pins Updated to clarify DDRMC_ONLY banks.
Drive Strength Control Added 2 mA.
X5IO IOB Pre-Emphasis and Receiver Equalization (CTLE)
  • Removed DFE from title.
  • Added paragraph about X5IO CTLE_EQ levels.
  • Updated Table 1.
Table 4 Removed DFE_EQ.
Table 5 Replaced RTT_40 , RTT_48, RTT_60, RTT_NONE (Default) with ODT.
X5IO IOB Supported Differential Standards and Attributes
  • Added sentence about MIPI_DPHY.
  • Updated description of MIPI_CPHY.
Figure 1 Renumbered CMPHY_OCTAD in lower bank.
Table 2
  • Updated Values and Description columns for DFE_EQ_M, DFE_EQ_S, DFE_H2_NEG_POL_M, DFE_H2_NEG_POL_S, DFE_H2_TAP_WEIGHT_M, and DFE_H2_TAP_WEIGHT_S.
  • Removed ISTANDARD_M, ISTANDARD_S, OSTANDARD_M, and OSTANDARD_S.
03/07/2025 Version 1.6
XP XPHY Updated bullet about XP IOL resources.
XP IOB Updated bullet about DCI reference resistors.
X5IO Features Added section.
X5IO IOB Added section.
X5IO PHY Added section.
Table 1 Updated description of CASCADE_<0-5>.
XP IOL Resources Reduced I/O interface speed to 250 Mb/s.
Corner Banks, DDRMC_ONLY, and PL Only Pins Added section.
Table 3 and Table 4 Removed IOBUFDS/IOBUFDSE3 allowed values and default for DC_BIAS attribute.
Calibrated Termination (Digitally Controlled Impedance) Updated first paragraph and note.
X5IO IOB Resources Added chapter.
X5IO PHY Resources Added chapter.
03/18/2024 Version 1.5
IO_VR Updated section.
Single Data Rate Flip-Flops and Uncalibrated IOB Delay Updated note about tristate control.
Figure 1 and Figure 1 Updated figure.
Table 2
  • Changed DIFF_TERM to DIFF_TERM_ADV.
  • Updated note about DQS_BIAS.
Table 4 and Table 3
  • Removed RTT_48 for LVSTL.
  • Updated RDRV_48_48 allowed value for OUTPUT_IMPEDANCE.
Table 5, Table 8, Table 2, and Table 6 Removed support for RTT_NONE.
Figure 1 Updated IOBUF_DCIEN.
Table 1 Added RTT_NONE to allowed values for ODT.
Table 4 Updated note 1.
Table 2 and Table 2 Removed VREF.
Adjusting Receiver VREF Levels
  • Added description of how to use XPIO_VREF successfully.
  • Clarified equation and example.
Table 1 Clarified description of VREF_NIB.
Calibrated Termination (Digitally Controlled Impedance) Removed specific reference to bank 700 to make applicable to more devices with IO_VR pins.
Differential Termination Attribute Updated description of differential termination.
XP IOB Pre-emphasis and Equalization Updated description of PRE_EMPHASIS attribute.
HD IOL Features Clarified ODELAY sharing between data and tristate.
Table 1 Removed output primitive support for LVDS, SLVS, and LVPECL.
10/21/2022 Version 1.4
FIFO Updated description of FIFO_RD_CLK.
Controlling FIFO Modes Added SYNC and BYPASS usage descriptions and timing waveforms.
Table 1 Clarified that PHY_WREN/PHY_RDEN must be deasserted during the reset sequence and when issuing a BS_RESET from the RIU interface.
Table 1
  • Updated description of 2-stage synchronizer for CONTINUOUS_DQS.
  • Rewrote description of DELAY_VALUE.
Uncalibrated IOB Delay Added description of shared clock in IOLOGIC.
Table 4 Added RTT_NONE to OUTPUT_IMPEDANCE.
Table 8 Added RTT_NONE for POD12 to ODT.
XP IOB Supported Differential Standards Updated table headers to reflect differential UNISIMs.
Table 3 and Table 6 Added RTT_NONE to ODT.
MIPI-DPHY Output Buffer Primitive Updated description of HSTX_I for OBUFDS_DPHY_COMP primitive.
Table 2 Updated HSTX_I port description for OBUFDS_DPHY_COMP primitive.
Table 1 Expanded description of ISTANDARD and VREF_NIB attributes.
XP IOB Pre-emphasis and Equalization Removed AC coupling requirement and clarified pre-emphasis usage.
HD IOL Features Added sentence about shared clocking resources on IOLOGIC site.
03/02/2022 Version 1.3
Bidirectional Datapath Removed inter-nibble clocking from first PHY_RDEN bullet.
FIFO Updated title of Figure 1 and added Figure 2.
Controlling Tristate Control Added Figure 1 and Figure 2.
Ports Added note about high-performance interfaces.
Controlling TX to RX Loopback Clarified inter-nibble and inter-byte clocking when using TX to RX loopback.
Table 21 Clarified crse_dly bs_reset latency in description of bit [14].
Table 1 Removed inter-byte clocking from description of PHY_RDEN.
Uncalibrated IOB Delay
  • Clarified explanation of per tap delay.
  • Added note explaining timing analysis considerations with the IDELAYE5/ODELAYE5.
XP IOB Primitives
  • Added IOBUFDS_COMP and OBUFDS_DPHY_COMP.
  • Updated OBUFDS_DPHY description.
XP IOB Supported Single-Ended Standards Expanded description of SSTL15 IOSTANDARD.
MIPI-DPHY Output Buffer Primitive
  • Added OBUFDS_DPHY_COMP primitive and port description.
  • Updated HSTX_I description in Table 2.
XPIO_VREF Primitive Added Table 1.
XP IOB Internal VREF Updated first paragraph.
Adjusting Receiver VREF Levels
Table 1 Added columns for estimated gain.
XP IOB Features, Attributes, and Constraints, IOSTANDARD, Drive, Slew Control and the VOH Attribute, and IBUF_LOW_PWR Attribute Updated sections.
HD IOL Features
  • Added description of data to tristate race condition.
  • Updated description of uncalibrated IOB delay.
HD IOB Resources Adjusted performance guidance for HDIO and modified data rate.
HD IOB Features Added IOSTANDARD constraint description.
04/02/2021 Version 1.2
XP XPHY Clarified that IOL and XPHY must be used independently, and that the nibble dictates inter-nibble clock capabilities.
XPHY Nibble
  • Updated sentence about XPHY NIBBLESLICEs.
  • In sections where CONTINUOUS_DQS = TRUE, changed "strobe" to "capture clock."
Bidirectional Datapath
  • Clarified that PHY_RDEN affects both inter-nibble and inter-byte clocking.
  • Added that PHY_RDEN must be set to 0 prior to issuing a bs_reset.
Clocking Clarified NIBBLESLICE[1]'s involvement in receiving a complementary clock.
Controlling Delays
  • Updated note about jumps greater than eight taps.
  • Updated note about interfaces with REFCLK_FREQUENCY below 500 MHz.
  • Added description of align_delay.
  • Added sentence about NIBBLESLICE[0].
  • Added paragraph before Figure 3.
FIFO Added SYNC and BYPASS modes.
Controlling Tristate Control Added note that the delay for the tri-state control must be updated through the RIU interface.
Table 2 Updated Controlled By column for delay calibration and VTC.
Controlling TX to RX Loopback Added sentence that TXRX_LOOPBACK_# is not supported when SERIAL_MODE = TRUE.
Controlling IBUF_DISABLE and DYN_DCI Added paragraph about how PHY_RDEN is translated to DYN_DCI/IBUF_DISABLE. Updated notes 1 and 2 in Table 1.
Register Interface Unit
  • Updated Figure 2.
  • Updated description of bit [1] in Table 4.
  • Added sentence about setting PHY_WREN = 0 to description of bit [2] in Table 4.
  • Added sentence about applying a bs_reset to description of bit [13] in Table 5 and Table 6, and bit [14] in Table 21.
  • Updated description of bits [5:0] in Table 23.
Table 1
  • Updated description of CE, CTRL_CLK, INC, LD, PHY_RDEN, RIU_WR_EN, RX_EN_VTC, TX_EN_VTC, and FIFO_EMPTY.
  • Updated clock domain of Q0, Q1, Q2, Q3, Q4, and Q5.
Table 1 Updated description of CONTINUOUS_DQS, FIFO_MODE_<0-5>, RX_CLK_PHASE_N, RX_CLK_PHASE_P, RX_GATING, and TXRX_LOOPBACK_<0-5>.
Reset Sequence Clarified that NIBBLESLICE[0] must be used for proper output delay calibration of each NIBBLESLICE in a nibble.
XPHY Usage Added paragraph about BLI flip-flops.
Table 2 Added note to explain when input VCCO levels can be modified.
XP IOB Supported Single-Ended Standards Updated JEDEC standard references to reflect 1.2V and 1.5V LVCMOS standards.
XP IOB IBUFDISABLE Updated description of SIM_DEVICE attributes.
Single Data Rate Flip-Flops Replaced NIBBLESLICE with IOL.
HD IOB Supported Single-Ended Standards Added JEDEC specifications JESD8-7A and JESD8-5A to include 2.5V and 1.8V LVCMOS standards.
Table 1, Table 2, Table 1, Table 2, Table 1, Table 2, Table 1, and Table 2 Clarified that IBUFDISABLE is not supported in HD IOB.
Table 1 Removed support for 2 mA from DRIVE attribute.
11/24/2020 Version 1.1
XP XPHY
  • Removed bullet about XPHY UNISIM primitive.
  • Updated bullet about QBC and DBC functionality.
Bidirectional Datapath and Controlling IBUF_DISABLE and DYN_DCI Added new sections.
Table 2 Updated Connection (RX) column for CLK_TO_LOWER, CLK_TO_UPPER.
Delays
  • Removed description of tap value from note.
  • Added sentence that CRSE delay cannot be controlled through the PL.
Controlling Delays Updated section and added Figure 3.
Controlling FIFO Modes Added note about not registering FIFO_EMPTY as part of the FIFO_RDEN = !FIFO_EMPTY connection.
Tristate Control Rewrote section.
Controlling Tristate Control Rewrote first sentence.
Table 2 Updated second bullet in Controlled By column for VTC.
Controlling IBUF_DISABLE and DYN_DCI Added PHY SM description and sequence.
Register Interface Unit
  • Added references to Ports and Attributes sections in most tables.
  • Updated description of bit [2] in Table 4.
Table 4 Updated description of bits [0], [1], and [2].
Table 5 Updated description of bit [13].
Table 23 Added new table.
Table 26 Updated description of bits [9:0].
Table 1 Updated description of PHY_RDEN, PHY_WREN, DYN_DCI, RST, TX_RST, and IBUF_DISABLE.
Table 1 Updated description of CONTINUOUS_DQS, ODT_SRC_<0-5>, RX_GATING, TX_INIT_<0-5>, and TX_INIT_TRI.
Reset Sequence Updated section, including both figures.
XPHY Usage Added Tcl commands to change time value of input and output delays of a NIBBLESLICE.
Table 4, Table 5, Table 6, Table 7, Table 8, Table 9, Table 1, Table 2, Table 3, Table 4, Table 5, Table 6, and Table 7 Removed OFFSET_CNTRL attribute.
Table 2 and Table 2 Updated description of OSC[3:0], OSC_EN[1:0], and VREF.
Table 1 Added VOH (DIFF_SSTL15 ONLY) attribute.
Table 4 Added note about bidirectional configuration on I/O standards.
Receiver Offset Control Removed section.
Differential Termination Attribute Added VCCO requirement for differential impedance block.
DQS_BIAS, DC_BIAS, and AC Coupling Updated DC_BIAS and AC Coupling Recommendations sections.
XP IOB Pre-emphasis and Equalization Updated first paragraph and Table 1.
HD IOL Features Updated DPLL section.
HD IOB Primitives Removed IBUF_IBUFDISABLE, IBUFDS_IBUFDISABLE, and IBUFDS_DIFF_OUT_IBUFDISABLE.
Single-Ended Input Buffer Primitives Removed IBUF_IBUFDISABLE throughout.
Figure 1 Added new figure.
Differential Input Buffer Primitives Replaced IBUFDISABLE with INTERMDISABLE throughout.
Differential Bidirectional Buffer Primitives Corrected primitive names throughout.
07/29/2020 Version 1.0
Initial release. N/A