RX Datapath

Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)

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1.5 English

The RX datapath is composed of:

Input delay
Input delays can delay incoming serialized data up to 512 taps (0–511 taps), with a minimum of 625 ps of available delay. Input delays can be increased to 1024 taps (0–1023 taps) for a minimum of 1250 ps of available delay by cascading the output delay of an XPHY NIBBLESLICE to the end of its input delay. For more information on cascading, see the CASCADE_<0–5> attribute.
The deserializer supports 1:8, 1:4, and 1:2 deserialization. This is determined by the RX_DATA_WIDTH attribute.
The receiver of an XPHY NIBBLESLICE has an 8-deep FIFO. The parallel data written to the FIFO is synchronized to the programmable logic clock domain of choice before passing to the programmable logic.

RX datapath latency changes depending on the data width (RX_DATA_WIDTH) and FIFO_MODE_x attribute. Refer to Controlling FIFO Modes for RX datapath latencies.

Important: Because each NIBBLESLICE routes to a specific pin, receiving a differential signal (regardless of whether clock or data) consumes the pins and RX datapaths of both NIBBLESLICEs.
Important: If receiving a strobe and RX_GATING = ENABLE, bitslip is not needed. For all other cases, bitslip is needed for word alignment.