XP IOL Clock Managers

Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)

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1.5 English

Each XPIO bank has four clock managers in or adjacent to the bank with the ability to phase shift the clock signal for optimal signal timing. In addition to the two XPLLs described in XP XPHY Architecture, an MMCM and DPLL can be used in the XP IOL to generate new clock frequencies and to eliminate skew between clock and data paths as they reach the IDDR and ODDR registers. More details on these features can be found in XP Bank Supporting Resources and Corner Banks.