The following table summarizes the clocks used by the X5IO PHY and X5PLL.
| Clock | Location | I/O | Description |
|---|---|---|---|
| PHY_CLK | CMPHY_OCTAD | Input | Fabric clock for CMPHY_OCTAD. See Clock Domains in Table 1 for more information. |
| PHY_RXFIFO_RDCLK[1:0] | CMPHY_OCTAD | Input | Clock from fabric for receiver FIFO clock. |
| RXFIFO_WR_CLK[1:0] | CMPHY_OCTAD | Output | Receiver FIFO write clock. Generated internally from the X5IO PHY from the strobe/capture clock. |
| XCV2PHY_RD_CLK<0 to 3> | CMPHY_OCTAD | Input | X5IO PHY clock from X5PHIO_XCVR_X2. |
| XCV2PHY_WR_CLK<0 to 3> | CMPHY_OCTAD | Input | X5IO PHY clock from X5PHIO_XCVR_X2. |
| Capture Clock (e.g. Strobe or DQS) |
X5IO PHY | Input | Source-synchronous RX clock used for data capture. Package pin must be connected to DIFF_P. Package pin site type must include XCC in the name. See Table 3 for routability rules for OCTADs. |
| PLL_CLK0 | X5PHIO_XCVR_X2 | Input | High-speed clock from X5PLL and X5PHIO_DCCIBUF. |
| PLL_CLK90 | X5PHIO_XCVR_X2 | Input | High-speed clock from X5PLL and X5PHIO_DCCIBUF. |
| CLKIN | X5PLL | Input | General clock input. When connecting directly to the package pin, the package pin site type must include GC in the name. |
| CLKOUTPHY_0 | X5PLL | Output | Dedicated X5IO PHY clock output. |
| CLKOUTPHY_90 | X5PLL | Output | Dedicated X5IO PHY clock output. |
X5IO PHY requires an X5PLL for proper operation. Each X5IO bank contains one X5PLL that must be used for the X5IO PHY.
The X5PLL has two dedicated clocks connected to the X5IO PHY for high-speed operation. CLKOUTPHY_0 and CLKOUTPHY_90 can connect to any X5PHIO_XCVR_X2 within the bank as shown. The X5PHIO_DCCIBUF is used by the X5IO Wizard for additional clock performance adjustments.
X5IO PHYs in every two banks (for example, 704 and 705) can be connected to either of the two X5PLLs within either of the banks.
Transmit interfaces rely on the X5PLL CLKOUTPHY_0 and CLKOUTPHY_90 for the serialization clocks. X5IO PHY requires DDR clock frequency for CLKOUTPHY_0 and CLKOUTPHY_90.
As an example, consider a TX interface running at 1000 Mb/s with a DATAWIDTH = 16. The X5PLL would need to be configured to generate 500 MHz for CLKOUTPHY_0 and CLKOUTPHY_90. The CLKOUT0 would be at 62.5 MHz to support the 16-bit parallel load of the transmit data.
Receiver interfaces that use SERIAL mode similarly rely on the X5PLL CLKOUT0 and CLKOUTPHY_90 for the capture clock. For SERIAL mode, because the X5PLL’s CLKOUT0 and CLKOUTPHY_90 do not have a fixed alignment to the incoming receiver data, additional circuitry is required to align the data and capture clock which is supplied by the X5IO Wizard.
Receiver interfaces that are used in source-synchronous interfaces use a combination of the X5PLL and the receiver’s capture clock. The X5PLL’s CLKOUTPHY_0 and CLKOUTPHY_90 are used during the reset sequence as a capture clock to calibrate the X5IO PHY. After the reset sequence is completed, the X5IO PHY switches to using the receiver’s capture clock to capture receive data and generate the FIFO_WR_CLK clock output. CLKOUTPHY_0 and CLKOUTPHY_90 are still used for monitoring fluctuations in voltage and temperature.
The receiver’s capture clock must be located in BIT2 of the OCTAD. The package pin that is connected to either the receiver’s capture clock or the clock input of the X5PLL requires dedicated routing resources. To determine if a package pin can be used for a receiver’s capture clock (XCC) or a clock input for the X5PLL (GC), check the package site name. In this case, the GC pins have additional routing resources and this is only to highlight the X5PLL routing capabilities.
| Package Pin Site | BIT | Clock Usage |
|---|---|---|
| IO_L0P_H0O0P0_700 | 0 | – |
| IO_L0N_H0O0P1_700 | 1 | – |
| IO_L1P_XCC_H0O0P2_700 | 2 | X5IO capture clock (single-ended or differential P-side) |
| IO_L1N_XCC_H0O0P3_700 | 3 | X5IO capture clock (differential N-side) |
| IO_L2P_H0O0P4_700 | 4 | – |
| IO_L2N_H0O0P5_700 | 5 | – |
| IO_L3P_GC_H0O0P6_700 | 6 | CMT clock such as the X5PLL’s CLKIN (single-ended or differential P-side) |
| IO_L3N_GC_H0O0P7_700 | 7 | CMT Clock such as the X5PLL’s CLKIN (differential N-side) |
The routing of the receiver’s capture clock between OCTADs is controlled by how the X5IO PHY Octads are connected. For the X5IO PHY the receiver's capture clock routing is controlled by how the X5PHIO_XCVR_X2 primitives are connected together by the X5IO Wizard and the Vivado tools.
The following table shows for a given OCTAD where the capture clock can route to. For example OCTAD0 can only route to OCTAD0 or OCTAD1. But if the capture clock is moved to OCTAD1, the capture clock can be routed to OCTAD0, OCTAD1, OCTAD2, or OCTAD3.
Capture clock routing is restricted to one full bank. Additional clock calibration can be performed by the X5IO Wizard.
| Capture Clock | Routes to OCTAD0 | Routes to OCTAD1 | Routes to OCTAD2 | Routes to OCTAD3 |
|---|---|---|---|---|
| OCTAD0 Capture Clock | YES | YES | NO | NO |
| OCTAD1 Capture Clock | YES | YES | YES | YES |
| OCTAD2 Capture Clock | YES | YES | YES | YES |
| OCTAD3 Capture Clock | NO | NO | YES | YES |