The MIPI D-PHY Controller has been verified using
both simulation and hardware testing. A highly parameterizable transaction-based simulation
test suite has been used to verify the core. The tests include:
- High-Speed data transmission
- High-Speed data reception
- Low-Power data transmission (LPDT)
- LPDT data reception
- Clock lane Ultra-Low Power State (ULPS) operation
- Data lane ULPS operation
- Triggers and escape mode commands
- Recovery from error conditions
- Register read and write access