Verification, Compliance, and Interoperability - 4.3 English

MIPI D-PHY LogiCORE IP Product Guide (PG202)

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Release Date
4.3 English
The MIPI D-PHY Controller has been verified using both simulation and hardware testing. A highly parameterizable transaction-based simulation test suite has been used to verify the core. The tests include:
  • High-Speed data transmission
  • High-Speed data reception
  • Low-Power data transmission (LPDT)
  • LPDT data reception
  • Clock lane Ultra-Low Power State (ULPS) operation
  • Data lane ULPS operation
  • Triggers and escape mode commands
  • Recovery from error conditions
  • Register read and write access