Shared Logic in Core - 4.3 English

MIPI D-PHY LogiCORE IP Product Guide (PG202)

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4.3 English
Select Include Shared Logic in core if:
  • You do not require direct control over the MMCM and PLL generated clocks
  • You want to manage multiple customizations of the core for multi-core designs
  • This is the first MIPI D-PHY core in a multi-core system

These components are included in the core, and their output ports are also provided as core outputs.

For SLAVE Mode with line rates of over 1500, and when you select Including Shared logic in the core.

Selecting Internal MMCM implements MMCM inside the core.

Selecting External MMCM does not implement the MMCM inside the core.

Required clocks need to be generated from the external MMCM and need to be connected to the core.