HS_TIMEOUT Register - 4.3 English

MIPI D-PHY LogiCORE IP Product Guide (PG202)

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4.3 English
The HS_TIMEOUT register (0x10 offset) is used as a watchdog timer in high-speed mode. This register is used as HS_TX_TIMEOUT (MIPI D-PHY TX core) or as HS_RX_TIMEOUT (MIPI D-PHY RX core). The following table shows the HS_TIMEOUT register bit description.
Table 1. HS_TIMEOUT Register Bit Description
Bits Name Access Default Value Description
31:0 HS_RX_TIMEOUT/HS_TX_TIMEOUT R/W 65,541 Maximum frame length in bytes. Valid range is 1,000 to 65,541. Timeout occurs for HS_RX_TIMEOUT/D-PHY_LANES at the RX data lanes in high speed mode. Timeout occurs for HS_TX_TIMEOUT/D-PHY_LANES at the TX data lanes in high speed mode.