Example 7: High-Speed Receive with Synchronization Error at D-PHY RX (Slave) Side - 4.3 English - PG202

MIPI D-PHY LogiCORE IP Product Guide (PG202)

Document ID
PG202
Release Date
2024-12-04
Version
4.3 English

The MIPI D-PHY RX core can detect a start-of-transmission (SoT) pattern with single-bit error. It is reported by the assertion of rxerrsoths for one clock cycle of rxbytehs along with the rxsynchs pulse. This behavior is shown in the following figure.

Figure 1. High-Speed Mode Data Receive with Synchronization Error at the D-PHY RX (Slave)