Example 5: D-PHY TX (Master) Clock Lane ULPS Operation - 4.3 English

MIPI D-PHY LogiCORE IP Product Guide (PG202)

Document ID
PG202
Release Date
2023-05-16
Version
4.3 English
This section describes a TX clock lane ULPS operation.
  1. The PPI drives txulpsclk to initiate the clock lane ULPS mode.
  2. The MIPI D-PHY TX core drives the clock lane ulpsactivenot (active-Low) to Low after the ULPS entry sequence is transmitted on the serial line.
  3. The PPI asserts the txulpsexit signal to exit from ULPS.
  4. The MIPI D-PHY TX core drives the ulpsactivenot High and drives MARK-1 on the serial lines.
  5. The PPI deasserts the txrequestesc after T_WAKEUP time has elapsed following deassertion of the ulpsactivenot signal.
The following figure shows the TX clock lane ULPS operation.
Figure 1. D-PHY TX (Master) ULPS Mode Operation for Clock Lane