- RX clock lane pins must be DBC, QBC and GC_QBC pins.
- It is advised to select the IO pins continuously without leaving any IO pairs
in the middle of D-PHY interface. The following figure shows the recommendation
message that appears in the GUI.
- D-PHY IP uses IO in Native mode. Using the left out IO’s in the nibble is not recommended. If this is necessary, refer to “Mixing Native and Non-Native Mode I/O in a Nibble” section in UltraScale Architecture SelectIO Resources User Guide (UG571).
- HSSIO internally uses few IO under certain IO selection scenarios for strobe propagation and this can be avoided by selecting IO continuously. Pin(s) used for Strobe propagation will be DBC, QBC or GC_QBC and it will restrict you to implement the multiple D-PHY interfaces.
- D-PHY with two different line rates can be implemented within IO bank and each D-PHY interface will use one PLL.
- All the lanes of a particular MIPI D-PHY instance need to be in the same HP IO bank, which the Pin Assignment tab of XGUI automatically controls for UltraScale+ devices.
- In case of multiple D-PHY instances sharing clocking resources, all such instances also need to be in the same HP IO bank.
- Any IO being placed along with D-PHY interface should have DCI IO standard because D-PHY IO uses MIPI_DPHY_DCI IO Standard.
- IO used for data lanes can be swapped in any order by keeping RX clock lane IO LOC unchanged.
The following table shows an example of a four 4-lane D-PHY interface that be implemented
in a single HP IO bank.
The following table shows an example of a eight 2-lane D-PHY interface that be
implemented in a single HP IO bank.
Interface | Signal Name | Byte Group | Pin Type |
---|---|---|---|
- | - | T3U_12 | - |
- | - | T3U_11 | N |
- | - | T3U_10 | P |
if3 | data_rxn[3] | T3U_9 | N |
if3 | data_rxp[3] | T3U_8 | P |
if3 | data_rxn[2] | T3U_7 | N |
if3 | data_rxp[2] | T3U_6 | P |
if3 | data_rxn[1] | T3L_5 | N |
if3 | data_rxp[1] | T3L_4 | P |
if3 | data_rxn[0] | T3L_3 | N |
if3 | data_rxp[0] | T3L_2 | P |
if3 | clk_rxn | T3L_1 | N |
if3 | clk_rxp | T3L_0 | P |
- | - | T2U_12 | - |
- | - | T2U_11 | N |
- | - | T2U_10 | P |
if2 | data_rxn[3] | T2U_9 | N |
if2 | data_rxp[3] | T2U_8 | P |
if2 | data_rxn[2] | T2U_7 | N |
if2 | data_rxp[2] | T2U_6 | P |
if2 | data_rxn[1] | T2L_5 | N |
if2 | data_rxp[1] | T2L_4 | P |
if2 | data_rxn[0] | T2L_3 | N |
if2 | data_rxp[0] | T2L_2 | P |
if2 | clk_rxn | T2L_1 | N |
if2 | clk_rxp | T2L_0 | P |
- | - | T1U_12 | - |
- | - | T1U_11 | N |
- | - | T1U_10 | P |
if1 | data_rxn[3] | T1U_9 | N |
if1 | data_rxp[3] | T1U_8 | P |
if1 | data_rxn[2] | T1U_7 | N |
if1 | data_rxp[2] | T1U_6 | P |
if1 | data_rxn[1] | T1L_5 | N |
if1 | data_rxp[1] | T1L_4 | P |
if1 | data_rxn[0] | T1L_3 | N |
if1 | data_rxp[0] | T1L_2 | P |
if1 | clk_rxn | T1L_1 | N |
if1 | clk_rxp | T1L_0 | P |
- | - | T0U_12 | - |
- | - | T0U_11 | N |
- | - | T0U_10 | P |
if0 | data_rxn[3] | T0U_9 | N |
if0 | data_rxp[3] | T0U_8 | P |
if0 | data_rxn[2] | T0U_7 | N |
if0 | data_rxp[2] | T0U_6 | P |
if0 | data_rxn[1] | T0L_5 | N |
if0 | data_rxp[1] | T0L_4 | P |
if0 | data_rxn[0] | T0L_3 | N |
if0 | data_rxp[0] | T0L_2 | P |
if0 | clk_rxn | T0L_1 | N |
if0 | clk_rxp | T0L_0 | P |
Interface | Signal Name | Byte Group | Pin Type |
---|---|---|---|
- | - | T3U_12 | - |
if7 | data_rxn[1] | T3U_11 | N |
if7 | data_rxp[1] | T3U_10 | P |
if7 | data_rxn[0] | T3U_9 | N |
if7 | data_rxp[0] | T3U_8 | P |
if7 | clk_rxn | T3U_7 | N |
if7 | clk_rxp | T3U_6 | P |
if6 | data_rxn[1] | T3L_5 | N |
if6 | data_rxp[1] | T3L_4 | P |
if6 | data_rxn[0] | T3L_3 | N |
if6 | data_rxp[0] | T3L_2 | P |
if6 | clk_rxn | T3L_1 | N |
if6 | clk_rxp | T3L_0 | P |
- | - | T2U_12 | - |
if5 | data_rxn[1] | T2U_11 | N |
if5 | data_rxp[1] | T2U_10 | P |
if5 | data_rxn[0] | T2U_9 | N |
if5 | data_rxp[0] | T2U_8 | P |
if5 | clk_rxn | T2U_7 | N |
if5 | clk_rxp | T2U_6 | P |
if4 | data_rxn[1] | T2L_5 | N |
if4 | data_rxp[1] | T2L_4 | P |
if4 | data_rxn[0] | T2L_3 | N |
if4 | data_rxp[0] | T2L_2 | P |
if4 | clk_rxn | T2L_1 | N |
if4 | clk_rxp | T2L_0 | P |
- | - | T1U_12 | - |
if3 | data_rxn[1] | T1U_11 | N |
if3 | data_rxp[1] | T1U_10 | P |
if3 | data_rxn[0] | T1U_9 | N |
if3 | data_rxp[0] | T1U_8 | P |
if3 | clk_rxn | T1U_7 | N |
if3 | clk_rxp | T1U_6 | P |
if2 | data_rxn[1] | T1L_5 | N |
if2 | data_rxp[1] | T1L_4 | P |
if2 | data_rxn[0] | T1L_3 | N |
if2 | data_rxp[0] | T1L_2 | P |
if2 | clk_rxn | T1L_1 | N |
if2 | clk_rxp | T1L_0 | P |
- | - | T0U_12 | - |
if1 | data_rxn[1] | T0U_11 | N |
if1 | data_rxp[1] | T0U_10 | P |
if1 | data_rxn[0] | T0U_9 | N |
if1 | data_rxp[0] | T0U_8 | P |
if1 | clk_rxn | T0U_7 | N |
if1 | clk_rxp | T0U_6 | P |
if0 | data_rxn[1] | T0L_5 | N |
if0 | data_rxp[1] | T0L_4 | P |
if0 | data_rxn[0] | T0L_3 | N |
if0 | data_rxp[0] | T0L_2 | P |
if0 | clk_rxn | T0L_1 | N |
if0 | clk_rxp | T0L_0 | P |