The following figure shows the Shared Logic tab of the Customize IP
interface.
Note: This tab is not
available for 7 series D-PHY RX configurations.
Figure 1. Shared Logic Tab
This tab allows you to select whether the MMCM and PLL are included in the core or in the example design. Following are the available options:
- Include Shared Logic in core
- Include Shared Logic in example design (default selection)
- MMCM Sharing Across the banks is available if you select Include Shared Logic in the core.