- Select the HP IO bank that has the VRP pin. DCI_CASCADE is allowed from HP IO bank of the same IO column in case the VRP pin is grounded for the selected HP IO bank.
- Select the IO pins continuously without leaving any IO pairs in the middle of D-PHY interface.
- Because D-PHY IP uses IO in Native mode, left out IO cannot be used by any other design and is unusable.
- D-PHY with two different line rates can be implemented within an IO bank and each D-PHY interface uses one PLL.
- All the lanes of a particular MIPI D-PHY instance need to be in the same HP IO bank, which the Pin Assignment Tab of XGUI automatically controls for UltraScale+.
- In the case of multiple MIPI D-PHY instances sharing clock resources, all such instances need to be in the same HP IO bank.
- IO used for clock lane and data lane(s) can be swapped in any order for D-PHY TX IP.