D-PHY TX Pin Rules - 4.3 English

MIPI D-PHY LogiCORE IP Product Guide (PG202)

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Release Date
4.3 English
  • Select the HP IO bank that has the VRP pin. DCI_CASCADE is allowed from HP IO bank of the same IO column in case the VRP pin is grounded for the selected HP IO bank.
  • Select the IO pins continuously without leaving any IO pairs in the middle of D-PHY interface.
  • Since D-PHY IP is using IO in Native mode, left out IO cannot be used by any other design and it will be unusable.
  • D-PHY with two different line rates can be implemented within IO bank and each D-PHY interface will use one PLL.
  • All the lanes of a particular MIPI D-PHY instance need to be in the same HP IO bank, which the Pin Assignment Tab of XGUI automatically controls for UltraScale+.
  • In a case of multiple MIPI D-PHY instances sharing clock resources, all such instances also need to be in the same HP IO bank.
  • IO used for clock lane and data lane(s) can be swapped in any order for D-PHY TX IP.