Core Specifics |
Supported Device Family
1
|
AMD Versal™
Adaptive SoC,
AMD UltraScale+™
Families, AMD Zynq™
UltraScale+™ MPSoC, AMD Zynq™ 7000 SoC, 7 series
FPGAs |
Supported User Interfaces |
PPI, AXI4-Lite
|
Resources |
Performance and Resource Use web
page
|
Provided with Core
|
Design Files |
Encrypted RTL |
Example Design |
Verilog |
Test Bench |
Verilog |
Constraints File |
Xilinx Design Contraints (XDC) |
Simulation Model |
Not Provided |
Supported S/W Driver |
N/A |
Tested Design Flows
2
|
Design Entry |
AMD Vivado™ Design Suite
|
Simulation |
For supported simulators, see the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973). |
Synthesis |
Vivado Synthesis |
Support |
Release Notes and Known Issues |
Master Answer Records: 54550
|
All Vivado IP Change Logs |
Master Vivado IP Change Logs: 72775
|
Support web
page
|
- For a complete list of supported devices, see
the AMD Vivado™
IP catalog.
- For the supported versions of the tools, see
the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973).
|