The HS_SETTLE register (0x30 offset,
0x48 to 0x60 offset) provides control to update the HS_SETTLE timing parameter for RX data
lanes. The following table provides the HS_SETTLE register bit description.
Bits | Name | Access | Default Value | Description |
---|---|---|---|---|
31:9 | Reserved | RO | 0 | Reserved |
8:0 | HS_SETTLE_NS | R/W | 135 + 10 UI | HS_SETTLE timing parameter in the number of core_clk
clocks. For example, to program 105 ns, then the value that needs to be programmed
is 105/5, that is, 21 (here 5 is 5 ns, that is, the time period of core_clk). This
value is applied for all data lanes and will only be applicable for D-PHY RX
configuration. Note: UI is unit interval.
|