HS_SETTLE Register - 4.3 English

MIPI D-PHY LogiCORE IP Product Guide (PG202)

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4.3 English
The HS_SETTLE register (0x30 offset, 0x48 to 0x60 offset) provides control to update the HS_SETTLE timing parameter for RX data lanes. The following table provides the HS_SETTLE register bit description.
Table 1. HS_SETTLE Register Bit Description
Bits Name Access Default Value Description
31:9 Reserved RO 0 Reserved
8:0 HS_SETTLE_NS R/W 135 + 10 UI HS_SETTLE timing parameter (ns). This value will be applied for all data lanes and will only be applicable for D-PHY RX configuration.
Note: UI is unit interval.