Resetting TX-Only Designs - 4.3 English

1. Assert the MIPI D-PHY TX IP core_rst.
2. Hold reset signals for a minimum of 40 core_clk cycles.
3. Deassert the MIPI D-PHY TX core_rst signal.
4. The MIPI D-PHY TX IP core initialization completes after a T_INIT_MASTER time of 1 ms and is indicated by the assertion of the stopstate signal.
5. At this point, the MIPI D-PHY RX IP core is ready to accept, and the MIPI D-PHY TX IP core is ready to send, data fed from the TX PPI interface.