The IDELAY Tap Value register (0x74 Offset) is
used to configure the IDELAY tap values in fixed mode for 7 series FPGAs. The tap values are programed dynamically during
the core operation. The core need not be disabled to program a different tap value. The
initial tap value for all lanes is same as the GUI parameter C_IDLY_TAP. The following
table shows the Idelay Tap Value register bit description.
| Bits | Name | Access | Default | Description |
|---|---|---|---|---|
| 31:29 | Reserved | RO | 0 | Reserved |
| 28:24 | Tap value for lane7 | R/W | IDELAY tap value from GUI | Programs the IDELAY tap value for lane7 |
| 23:21 | Reserved | RO | 0 | Reserved |
| 20:16 | Tap value for lane6 | R/W | IDELAY tap value from GUI | Programs the IDELAY tap value for lane6 |
| 15:13 | Reserved | RO | 0 | Reserved |
| 12:8 | Tap value for lane5 | R/W | IDELAY tap value from GUI | Programs IDELAY Tap value for lane5 |
| 7:5 | Reserved | RO | 0 | Reserved |
| 4:0 | Tap value for lane4 | R/W | IDELAY tap value from GUI | Programs IDELAY Tap value for lane4 |
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