Hardware Validation - 4.3 English

MIPI D-PHY LogiCORE IP Product Guide (PG202)

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Release Date
4.3 English

The MIPI D-PHY Controller is tested in hardware for functionality, performance, and reliability using AMD evaluation platforms. The MIPI D-PHY Controller verification test suites for all possible modules are continuously being updated to increase test coverage across the range of possible parameters for each individual module.

A series of MIPI D-PHY Controller test scenarios are validated using the AMD Zynq™ UltraScale+™ MPSoC ZCU102 development board. This board allows the prototyping of system designs where the MIPI D-PHY Controller is used for high-speed serial communication between two boards.

7 series FPGAs do not have native MIPI IOB support: target the HP/HR IO bank for 7 series FPGAs and the XPIO bank for AMD Versal™ devices.

For more information, refer D-PHY Solutions (XAPP894) .

A series of interoperability test scenarios are listed in the following table that are validated using different core configurations and resolutions.

Table 1. MIPI CSI2 Sensor Interoperability Testing
Sensor Board/Device Tested Configuration Resolution
Omnivision OV13850 ZCU102/xczu9eg-ffvb1156-2-i-es2
  • D-PHY RX
  • 1200 Mbps
  • 1, 2, 4 Lanes
480p@60 fps, 720p@60 fps, 1080p@60 fps, 4k@30 fps
Sony IMX274 ZCU102/xczu9eg-ffvb1156-2-i-es2
  • D-PHY RX
  • 1440 Mbps
  • 4 Lanes
All supported modes by sensor
Sony IMX224 ZCU102/xczu9eg-ffvb1156-2-i-es2
  • D-PHY RX
  • 149 Mbps, 594 Mbps
  • 1, 2, 4 Lanes
All-pixel (QVGA) and Window cropping modes
Sony IMX274 ZC702/xc7z020clg484-1
  • D-PHY RX
  • 576 Mbps
  • 4 Lanes
1080p@60 fps
The following table lists the interoperability test, validated using the MIPI DSI display.
Table 2. MIPI DSI Display Interoperability Testing
Sensor Board/Device Tested Configuration Resolution
B101UAN01.7 ZCU102/xczu9eg-ffvb1156-2-e
  • D-PHY TX
  • 1000 Mbps
  • 4 Lanes
1920x1200@60 fps