To reset the MIPI D-PHY TX and RX core
in a system, perform the following procedure:
- Assert
core_rst
of MIPI D-PHY TX IP core for minimum 40core_clk
cycles. - Assert
core_rst
of MIPI D-PHY RX IP core for minimum 40core_clk
cycles. - Release the MIPI D-PHY RX
core_rst
signal.Note: When there are multiple instances of D-PHY within the same bank, or when there are TX and RX in same bank, perform the reset removal at same time. - Release the MIPI D-PHY TX
core_rst
signal.Note: When there are multiple instances of D-PHY within the same bank, or when there are TX and RX in same bank, perform the reset removal at same time. - The MIPI D-PHY RX IP core initialization happens after a T_INIT_SLAVE time of 100 μs and is indicated by the assertion of stopstate.
- The MIPI D-PHY TX IP core initialization happens after a T_INIT_MASTER time if 1 ms and is indicated by stopstate assertion.
- At this point, the MIPI D-PHY TX IP core is ready to accept data from the TX PPI interface.
Note: The impact of the assertion of
core_rst
on the MIPI D-PHY core is
the same as the assertion of the DPHY_EN bit of the CONTROL register.