General Design Guidelines - 4.3 English

MIPI D-PHY LogiCORE IP Product Guide (PG202)

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4.3 English

This section describes the steps required to turn a MIPI D-PHY core into a fully functioning design with user-application logic.

Important: Not all implementations require all of the design steps listed here. Follow the logic design guidelines in this manual carefully.

When there are multiple instances of MIPI interfaces or other IP sharing the same IO bank, initialize all interfaces in the same HP IO bank at the same time. This includes resetting all instances at the same time. When there are multiple DPHY TX instances, you cannot mix MIPI D-PHY TX with lane-rate (>1501 Mbps and <=1500 Mbps) in the same HP IO bank. For more information on implementing multiple interfaces in the same HP IO Bank, see UltraScale Architecture SelectIO Resources User Guide (UG571).