The DL_STATUS register (0x1C to 0x28,
0x64 to 0x70 offset) provides data lane status and state machine control. The following table
provides the DL_STATUS register bit description.
| Bits | Name | Access | Default Value | Description |
|---|---|---|---|---|
| 31:16 | PKT_CNT | RO | 0 | Number of packets received or transmitted on the data lane. This field is updated using the rxbyteclkhs clock and the RX clock lane must be in high-speed mode when reset is applied to the D-PHY RX IP. Otherwise, this value does not get reset for MIPI D-PHY RX IP configuration. |
| 15:7 | Reserved | RO | 0 | Reserved. |
| 6 | STOP_STATE | RO | 0 | Data lane is in the Stop state. |
| 5 | ESC_ABORT | R/W1C | 0 | This bit is set after the Data Lane Escape Timeout (Escape Mode Timeout in case of RX, or Escape Mode Silence Timeout in case of TX) is elapsed. Write-to-1 clears this bit. |
| 4 | HS_ABORT | R/W1C | 0 | Set after the Data Lane High-Speed Timeout (HS_TX_TIMEOUT or HS_RX_TIMEOUT) has elapsed. Write to 1 clears this bit. |
| 3 | INIT_DONE | RO | 0 | Set after the lane has completed initialization. |
| 2 | ULPS | RO | 0 | Set to 1 when the core is in ULPS mode. |
| 1:0 | MODE | RO | 0 |
|