The following figure shows the MIPI D-PHY RX
(Slave) core architecture for AMD UltraScale+™
families
and AMD Zynq™
UltraScale+™ MPSoC devices. The RX core is
partitioned into three major blocks:
- RX PCS Logic
- Interfaces with PHY and delivers PHY-Protocol Interface (PPI)-compliant transactions such as High-Speed and Escape mode Low-Power Data Transmission (LPDT) packets. It is also responsible for lane initialization, start-of-transmission (SoT) detection, and clock recovery in escape mode.
- RX PHY Logic
- Performs clock recovery in high-speed mode and de-serialization. Integrates the BITSLICE_CONTROL and RX_BITSLICE in native mode and D-PHY compatible I/O block.
- Register Interface
- Optional AXI4-Lite register interface to control protocol mandatory timers and registers.
Figure 1. MIPI D-PHY RX (Slave) Core Architecture for UltraScale+ Families
The following figure shows the MIPI D-PHY RX (Slave) Core Architecture for the 7 series FPGA families.
Figure 2. MIPI D-PHY RX (Slave) Core Architecture for 7 Series FPGA
Families
The following figure shows the architecture for MIPI D-PHY RX (Slave) Core Architecture for Versal device families
Figure 3. MIPI D-PHY RX (Slave) Core Architecture for Versal Device Families
