D-PHY Protocol Checks - 4.3 English

MIPI D-PHY LogiCORE IP Product Guide (PG202)

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4.3 English
  • Ensure that HS and Escape transactions are initiated when core is in StopState.
  • Check the enable from PPI is connected and it is active-High during operation.
  • Ensure bytes transferred or received are within HS_TIMEOUT in case of HS mode and ESC_TIMEOUT in case of LPDT.
  • Ensure HS_SETTLE of D-PHY RX matches with the HS_PREPARE + HS_ZERO of D-PHY TX.
  • Check received LP transactions are at least of 20 ns duration or more.
  • Monitor PPI error signals such as errsoths and errsotsynchs. Excessive errsotsynchs indicates either HS_SETTLE parameter tuning or signal integrity issues on the D-PHY RX link.
  • Ensure that there is no skew between different D-PHY RX lanes within same MIPI D-PHY interface. D-PHY RX IP does not perform any inter-lane skew adjustment operations on the received high-speed data. This is left to a higher level protocol layer such as CSI-2 RX.