- Compliant to MIPI Alliance Standard for D-PHY Specification, version 2.0.
- Synchronous transfer at high-speed mode with a bit rate of 80-3200 Mb/s depending on the device family and speed grade. For details about line rate support, refer to the respective data sheets.
- One clock lane and up to four data lanes for TX configuration.
- One clock lane and up to eight data lanes for RX configuration.
- Asynchronous transfer at low-power mode with a bit rate of 10 Mb/s.
- Ultra low-power mode, and high-speed mode for clock lane.
- Ultra low-power mode, high-speed mode, and escape mode for data lane.
- PHY-Protocol Interface (PPI) to connect CSI-2 and DSI applications.
- Optional AXI4-Lite interface for register access.