High Frequency Clock Transmission - 4.3 English

MIPI D-PHY LogiCORE IP Product Guide (PG202)

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4.3 English

The clock lane transmits a low-swing, differential high-speed DDR clock from the master to the slave for high-speed data transmission. It is controlled by the protocol through the clock lane PPI. The clock signal has quadrature-phase with a toggling bit sequence on the data lane.