Pin Rules for 7 Series FPGAs - 4.3 English

MIPI D-PHY LogiCORE IP Product Guide (PG202)

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4.3 English
This section describes the pin rules for 7 series FPGAs:
  • Non-continuous IO usage is allowed for D-PHY TX and RX interfaces but not recommended.
  • Restrict the IO selection within the single IO bank.
  • Select SRCC/MRCC pins for D-PHY RX clock lane.