Resetting RX-Only Designs - 4.3 English

MIPI D-PHY LogiCORE IP Product Guide (PG202)

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4.3 English
  1. Assert the MIPI D-PHY RX IP core_rst.
  2. Hold the reset signals for a minimum of 40 core_clk cycles.
  3. Deassert the MIPI D-PHY RX core_rst signal.
  4. The MIPI D-PHY RX IP core initialization completes after a T_INIT_SLAVE time of 100 μs. This is indicated by the assertion of the stopstate signal.
  5. At this point, the MIPI D-PHY RX IP core is ready to accept MIPI D-PHY serial data from the TX partner.