Required Constraints
This section defines the additional constraint requirements for the core. Constraints are provided with a Design Constraints (XDC) file. An XDC is provided with the HDL example design to give a starting point for constraints for your design.
Device, Package, and Speed Grade Selections
- Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics (DS922)
- Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS923)
- Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925)
- Artix UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS931)
- Versal AI Core Series Data Sheet: DC and AC Switching Characteristics (DS957)
Clock Frequencies
core_clk
should be specified as follows:
create_clock -name core_clk -period 5.000 [get_ports core_clk]
This
constraint defines the frequency of core_clk
that is supplied to the MMCM
and PCS logic.Clock Management
The MIPI D-PHY Controller uses an MMCM to generate the general interconnect clocks, and the PLL is used to generate the serial clock and parallel clocks for the PHY. The input to the MMCM is constrained as shown in Clock Frequencies. No additional constraints are required for the clock management.
Clock Placement
This section is not applicable for this IP core.
Banking
Transceiver Placement
This section is not applicable for this IP core.
I/O Standard and Placement
MIPI standard serial I/O ports should use MIPI_DPHY_DCI for the I/O standard in the XDC file for AMD UltraScale+™ families. The LOC and I/O standards must be specified in the XDC file for all input and output ports of the design. UltraScale+ MIPI D-PHY IP generates the IO pin LOC for the pins that are selected during IP customization. No IO pin LOC are provided for 7 series MIPI D-PHY IP designs. You have to manually select the clock capable IO for 7 series RX clock lane and restrict the IO selection within the IO bank for both D-PHY TX and D-PHY RX IP configurations.
VRP
pin connected for UltraScale+ MIPI
D-PHY TX/RX IP core. If VRP
pin is present in other IO bank
in the same IO column of the device, the following DCI_CASCADE XDC constraint should be
used. For example, IO bank 65 has a VRP
pin and the D-PHY
TX IP is using the IO bank
66.set_property DCI_CASCADE {66} [get_iobanks 65]
For more information on MIPI_DPHY_DCI IO standard and VRP
pin requirements, see the
UltraScale
Architecture SelectIO Resources User Guide (UG571).