HS Data Transfer - 4.3 English

MIPI D-PHY LogiCORE IP Product Guide (PG202)

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4.3 English

HS data can be transferred as soon as the HS clock transmission has started. The txrequesths signal on the TX data lane starts the data transfer. A value of 2’b01 in the MODE field of the DL_STATUS register confirms that the data lane is in HS mode. The PKT_CNT field of the DL_STATUS register provides the numbers of packets transmitted or received by the data lane. The HS mode PPI signals can also be used to monitor the HS data transfer. Each txrequesths is counted as one packet in the D-PHY TX and each rxactivehs with a rxsynchs pulse is considered as one packet in the D-PHY RX. Note that the D-PHY RX also counts erroneous transactions such as errsoths and errsotsynchs.

You can start with a small number of packets from the D-PHY TX and check whether the PKT_CNT of both the D-PHY TX and D-PHY RX match. Ensure that all of the control mode sequences are captured without any errors and that the errcontrol signal of the PPI RX is asserted if any erroneous control sequence is received on the serial lines. The HS_ABORT field in the DL_STATUS register is asserted if the D-PHY RX is receiving more bytes than the HS_TIMEOUT programmed value.

Monitor errsoths and errsotsynchs and tune the HS_SETTLE of D-PHY RX IP after making sure that there are no signal integrity issues. HS_SETTLE of D-PHY RX can be changed through AXI-4 Lite register interface and user can set desired value of HS_SETTLE during IP generation using HS_SETTLE_NS hidden user parameter.