The high-speed clock is transmitted on
the D-PHY TX clock lane. The assertion of
txrequesths on the TX clock lane
starts the clock transmission. A value of 2’b01 in the MODE field of the
CL_STATUS register confirms the HS clock transfer. The cl_rxclkactivehs PPI
signal also can be used to confirm the HS clock reception in the D-PHY RX.