HS Clock Transfer - 4.3 English

MIPI D-PHY LogiCORE IP Product Guide (PG202)

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4.3 English
The high-speed clock is transmitted on the D-PHY TX clock lane. The assertion of txrequesths on the TX clock lane starts the clock transmission. A value of 2’b01 in the MODE field of the CL_STATUS register confirms the HS clock transfer. The cl_rxclkactivehs PPI signal also can be used to confirm the HS clock reception in the D-PHY RX.