CONTROL Registers - 4.3 English - PG202

MIPI D-PHY LogiCORE IP Product Guide (PG202)
Document ID
PG202
Release Date
2024-12-04
Version
4.3 English
The following table shows the CONTROL register (0x0 offset) bit mapping and description. Writing a 1 to SRST resets the MIPI D-PHY core. For the soft reset impact on the MIPI D-PHY core, see Reset Coverage table. The MIPI D-PHY core functions only when the DPHY_EN bit is set to 1 (by default).
Table 1. CONTROL Register Bit Description
Bits Name Access Default Value Description
31:2 Reserved RO 0 Reserved.
1 DPHY_EN R/W 1 Enable bit for D-PHY.
  • 1: D-PHY controller is enabled.
  • 0: D-PHY controller is disabled.
0 SRST R/W 0

Soft reset for D-PHY Controller.

If 1 is written to this bit, the D-PHY controller fabric logic and status registers are reset.