This section describes low-power data transmission operation.
- For low-power data transmission, the
txclkesc
signal is used. The PPI directs the data lane to enter low-power data transmission escape mode by assertingtxrequestesc
and settingtxlpdtesc
High. - The low-power transmit data is transferred on the
txdataEsc[7:0]
whentxvalidesc
andtxreadyesc
are both active at a rising edge oftxclkesc
. The byte is transmitted in the time after thetxdataesc
is accepted by the MIPI D-PHY TX core (txvalidesc
andtxreadyesc
are High) and therefore thetxclkesc
continues running for some minimum time after the last byte is transmitted. - The PPI knows the byte transmission is finished when
txreadyesc
is asserted. - After the last byte has been transmitted, the PPI deasserts
txrequestesc
to end the low-power data transmission. This causestxreadyesc
to return Low, after which thetxclkesc
clock is no longer needed.
The following figure shows the low-power data transmission operation.
Figure 1. Low-Power Data Transfer from D-PHY TX (Master)