Example 2: Low-Power Data Transfer from D-PHY TX (Master) Side - 4.3 English

MIPI D-PHY LogiCORE IP Product Guide (PG202)

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4.3 English
This section describes low-power data transmission operation.
  1. For low-power data transmission, the txclkesc signal is used. The PPI directs the data lane to enter low-power data transmission escape mode by asserting txrequestesc and setting txlpdtesc High.
  2. The low-power transmit data is transferred on the txdataEsc[7:0] when txvalidesc and txreadyesc are both active at a rising edge of txclkesc. The byte is transmitted in the time after the txdataesc is accepted by the MIPI D-PHY TX core (txvalidesc and txreadyesc are High) and therefore the txclkesc continues running for some minimum time after the last byte is transmitted.
  3. The PPI knows the byte transmission is finished when txreadyesc is asserted.
  4. After the last byte has been transmitted, the PPI deasserts txrequestesc to end the low-power data transmission. This causes txreadyesc to return Low, after which the txclkesc clock is no longer needed.
The following figure shows the low-power data transmission operation.
Figure 1. Low-Power Data Transfer from D-PHY TX (Master)