AXI4-Lite Interface Debug - 4.3 English

MIPI D-PHY LogiCORE IP Product Guide (PG202)

Document ID
Release Date
4.3 English
Read from a register that does not have all 0s as a default to verify that the interface is functional. Output s_axi_arready asserts when the read address is valid, and output s_axi_rvalid asserts when the read data/response is valid. If the interface is unresponsive, ensure that the following conditions are met:
  • The s_axi_aclk and aclk inputs are connected and toggling.
  • The interface is not being held in reset, and s_axi_areset is an active-Low reset.
  • The interface is enabled, and s_axi_aclken is active-High (if used).
  • The main core clocks are toggling and that the enables are also asserted.
  • If the simulation has been run, verify in simulation and/or a Vivado Design Suite debug feature captures that the waveform is correct for accessing the AXI4-Lite interface.