D-PHY TX IP supports active lanes. The following table lists ports associated with active lane support.
Signal | Direction | Clock Domain | Description |
---|---|---|---|
active_lanes_in[<n-1>:0] 1 | Input | core_clk | Input to specify active lanes. This feature is available for D-PHY TX multi-lane configuration. Bits from LSB to MSB corresponds to TX Data lane 0 to 3. |
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