Active Lane Support Signals - 4.3 English

MIPI D-PHY LogiCORE IP Product Guide (PG202)

Document ID
Release Date
4.3 English

D-PHY TX IP supports active lanes. The following table lists ports associated with active lane support.

Table 1. Active Lane Support Signal
Signal Direction Clock Domain Description
active_lanes_in[<n-1>:0] 1 Input core_clk Input to specify active lanes. This feature is available for D-PHY TX multi-lane configuration. Bits from LSB to MSB corresponds to TX Data lane 0 to 3.
  1. <n> is the data lane number.