The MIPI D-PHY RX core reports the multi-bit error on the SoT pattern by
asserting rxerrsotsynchs
for one clock cycle of rxbyteclkhs
. This scenario indicates that the SoT pattern is
corrupted. Note that rxsynchs
is not asserted. Received
payload is passed on to the PPI. This behavior is shown in the following figure.
Figure 1. High-Speed Mode Data Receive with Loss of Synchronization at the D-PHY
RX (Slave)