Endianness Details - 4.3 English

MIPI D-PHY LogiCORE IP Product Guide (PG202)

Document ID
PG202
Release Date
2023-05-16
Version
4.3 English
All registers are in little endian format, as shown in the following table.
Table 1. 32-bit Little Endian Example
Byte Address Offset Bit Boundaries
Byte 0 0x0 [7:0]
Byte 1 0x1 [15:8]
Byte 2 0x2 [23:16]
Byte 3 0x3 [31:24]
Table 2. MIPI D-PHY Core Register Space
Offset Name Width Access Description
0x0 CONTROL 32-bit R/W Enable and soft reset control for PHY.
0x4 IDELAY_TAP_VALUE 32-bit R/W To program the tap values in fixed mode of calibration in 7 series D-PHY RX configuration for lanes 1 to 4.
0x8 INIT 32-bit R/W Initialization timer.
0xC Reserved 32-bit N/A N/A
0x10 HS_TIMEOUT 32-bit R/W Watchdog timeout in high-speed mode. Time from SoT to EoT is taken into account for the timer elapse. This register is available if the Enable HS and ESC Timeout Counters/Registers checkbox is selected in the Vivado IDE. HS_RX_TIMEOUT is used for RX (slave) HS_TX_TIMEOUT is used for TX (master)
0x14 ESC_TIMEOUT 32-bit R/W Protocol specific. In escape mode, if line stays in LP-00 longer than this time period the core generates a timeout and goes to Stop state. This register is available if the Enable HS and ESC Timeout Counters/Registers checkbox is selected in the Vivado IDE. This register is used as Escape Mode Timeout in RX, and Escape Mode Silence Timeout in TX. Escape Mode Timeout should be greater than Escape Mode Silence Timeout.
0x18 CL_STATUS 32-bit RO Status register for PHY error reporting for clock Lane.
0x1C to 0x28 DL0_STATUS 32-bit RO Status registers for PHY error reporting for data lanes 1 to 4.
DL1_STATUS 32-bit RO
DL2_STATUS 32-bit RO
DL3_STATUS 32-bit RO
0x30 HS_SETTLE 32-bit R/W HS_SETTLE timing control for lane 1.
0x34 to 0x44 Reserved 32-bit N/A N/A
0x48 to 0x60 HS_SETTLE 32-bit R/W HS_SETTLE timing control for lanes 2 to 8.
0x64 to 0x70 DL4_STATUS 32-bit RO Status registers for PHY error reporting for data lanes 5 to 8.
DL5_STATUS 32-bit RO
DL6_STATUS 32-bit RO
DL7_STATUS 32-bit RO
0x74 IDELAY_TAP_VALUE 32-bit R/W To program the tap values in fixed mode of calibration in 7 series D-PHY RX configuration for lanes 5 to 8.