Lane Initialization - 4.3 English

MIPI D-PHY LogiCORE IP Product Guide (PG202)

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4.3 English
After the assertion of power-on reset, MMCM lock followed by PLL lock should be asserted by the core. Monitor the mmcm_lock_out and pll_lock_out signals for the lock status. The serial lines of clock lane and data lane(s) should be driven with LP-11 for a period of T_INIT. The T_INIT value of the D-PHY RX should be 50% to 80% of the T_INIT value of the D-PHY TX. Bit 3 of the CL_STATUS or DL_STATUS registers confirm the completion of initialization. When the D-PHY core completes the initialization, stopstate is asserted on the PPI. Bit 4 of the CL_STATUS register and bit 6 of the DL_STATUS register indicate the Stop state.