Ultra-Low Power State - 4.3 English

MIPI D-PHY LogiCORE IP Product Guide (PG202)

Document ID
PG202
Release Date
2023-05-16
Version
4.3 English

This is one type of escape mode and is supported by both the clock lane and data lane. You can exit the ultra low power state by doing the following:

  • If the D-PHY RX ULPS WAKEUP counter for 1ms time option is selected, D-PHY TX must send the Mark-1 (LP-10) state for a duration of 1ms or longer, then drive the stop-state to make RX exits from the ULPS state.
  • If the D-PHY RX ULPS WAKEUP counter for 1ms time option is not selected, then D-PHY RX IP checks only for the Mark-1 (LP-10) transition to exit from the ULPS mode.