D-PHY RX IP includes calibration logic for 7 series FPGA families. The following table lists ports associated with the calibration logic.
Signal | Direction | Clock Domain | Description |
---|---|---|---|
dlyctrl_rdy_out | Output | N/A | Ready signal output from IDEALYCTRL, stating delay values are adjusted as per vtc changes. |
dlyctrl_rdy_in | Input | N/A | Ready signal input to IDELAYCTRL See 'Include IDELAYCTRL in Core' in the Core Configuration Tab section. |