INIT Register - 4.3 English

MIPI D-PHY LogiCORE IP Product Guide (PG202)

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4.3 English
The INIT register (0x8 offset) is used for lane initialization. The following table shows the register bit description.
Table 1. INIT Register Bit Description
Bits Name Access Default Value Description
31:0 T_INIT R/W
  • RX D-PHY IP:100 μs (32'h186A0)
  • TX D-PHY IP:1 ms (32'hF4240)
Initialization timer value in ns.