Example 4: D-PHY TX (Master) Data Lane ULPS Operation - 4.3 English - PG202

This section describes a TX data lane ULPS operation.

1. The PPI drives txrequestesc High to initiate the ULPS entry request. The txulpsesc signal is asserted for one txclkesc cycle.
2. The MIPI D-PHY TX core drives the data lane ulpsactivenot (active-Low) to Low which indicates that the ULPS command is transmitted on the serial lines.
3. The PPI drives the txulpsexit pulse to start the ULPS exit operation.
4. The MIPI D-PHY TX core responds by deasserting the ulpsactivenot signal and starts transmitting MARK-1 on the line for T_WAKEUP time.
5. The PPI deasserts the txrequestesc after T_WAKEUP time has elapsed following the deassertion of the ulpsactivenot signal.

The following figure shows TX data lane ULPS operation.